97SD3232 datasheet(19/39 Pages) MAXWELL

19 / 39 page

97SD3232

All data sheets are subject to change without notice

1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM

01.11.05 Rev 2

Operation of the SDRAM

The following section shows operation examples of 97SD3232.

Note: The SDRAM should be used according to the product capability ( See Pin Description and AC

Characteristics.)

Read/Write Operations:

Bank Active: Before executing a read or write operation, the corresponding bank and the row address must

be activated by the bank active (ACTV) command. An interval of t

RCD is required between the bank active

command input and the following read/write command input.

Read operation: A read operation starts when a read command is input. The output buffer becomes Low-Z

in the (CAS latency - 1) cycle after read command set. The SDRAM can perform a burst read operation.

The burst length can be set to 1, 2, 4, or 8. The start address for a burst read is specified by the column

address and the bank select address (BA0/BA1) at the read command set cycle. In a read operation, data

output starts after the number of clocks specified by the CAS latency. The CAS latency can be set to 2 or 3.

When the burst length is 1, 2, 4, or 8, the D

OUT buffer automatically becomes High-Z at the next clock after

the successive burst-length data has been output.

The CAS latency and burst length must be specified at the mode register.

97SD3232 Datasheet(PDF) 19 Page - Maxwell Technologies