IS25LP064A-RGLA1 datasheet(27/99 Pages) ISSI

27 / 99 page

IS25LP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

11/06/2015

FAST READ QPI OPERATION (FRD QPI, 0Bh)

The FAST READ QPI (FRD QPI) instruction is used to read memory data at up to a 133MHz clock.

The FAST READ QPI instruction code (2 clocks) is followed by three address bytes (A23-A0

—6clocks) and 6

dummy cycles (configurable, default is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each bit

latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2, IO1

and IO0 lines, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FAST READ QPI instruction. The FAST

READ QPI instruction is terminated by driving CE# high (VIH).

If the FAST READ QPI instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the

instruction is ignored without affecting the current cycle.

Table 8.3 Instructions that Fast Read QPI sequence is applied to

Instruction Name

Operation

Hex Code

FRQIO

Fast Read Quad I/O

EBh

RDUID

Read Unique ID

4Bh

RDSFDP

SFDP Read

5Ah

IRRD

Read Information Row

68h

Figure 8.3 Fast Read QPI Sequence

0Bh

CE#

SCK

IO[3:0]

6 Dummy Cycles

3-byte Address

...

Mode 3

Mode 0

23:20

7:4

3:0

7:4

3:0

Data 1

Data 2

19:16 15:12 11:8

7:4

3:0

...

Instruction

Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.10 Read

Dummy Cycles.

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