AWR2243_V01 datasheet(13/62 Pages) TI

13 / 62 page

Table 7-1. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

NUMBER

TYPE

DEFAULT PULL

STATUS(1)

DESCRIPTION

Reserved

RESERVED

R4, R5

—

Reserved. For debug purposes, it is recommended to

have test points on these pins.

Reset

NRESET

P12

—

Power on reset for chip. Active low.

The NRESET needs to be pulled low for a minimum

of 20 μsec to ensure proper device reset.

WARM_RESET(3)

N12

Open Drain

Open-drain fail-safe warm reset signal. Can be used

as a status signal that the device is going through

reset.

Sense on Power

SOP2

P13

—

The SOP pins are driven externally (weak drive) and

the AWR device senses the state of these pins during

bootup to decide the bootup mode. After boot the

same pins have other functionality.

[SOP2 SOP1 SOP0] = [0 0 1] -> Functional SPI mode

[SOP2 SOP1 SOP0] = [1 0 1] -> Flashing mode

[SOP2 SOP1 SOP0] = [0 1 1] -> debug mode

[SOP2 SOP1 SOP0] = [1 1 1] -> Functional I2C mode

SOP1

P11

—

SOP0

J13

—

Safety

NERROR_OUT

Open Drain

Open-drain fail-safe output signal. Connected to

PMIC/Processor/MCU to indicate that some severe

criticality fault has happened. Recovery would be

through reset.

NERROR_IN

Open Drain

Fail-safe input to the device. Error output from any

other device can be concentrated in the error

signaling monitor module inside the device and

appropriate action can be taken by firmware

JTAG

TMS

L13

Pull Up

JTAG port for TI internal development.

For debug purposes, it is recommended to have test

points on these pins.

TCK

M13

Pull Down

TDI

H13

Pull Up

TDO

J13

—

Reference

oscillator

CLKP

E14

—

In XTAL mode: Differential port for reference crystal

In External clock mode: Single ended input reference

clock port (Output CLKM is grounded in this case)

CLKM

F14

—

Band-gap

voltage

VBGAP

B10

—

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AWR2243

SWRS223A – FEBRUARY 2020 – REVISED AUGUST 2020

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