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AS9C25512M2018L Datasheet(PDF) 12 Page - Alliance Semiconductor Corporation

Part # AS9C25512M2018L
Description  2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
PDF  30 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS9C25512M2018L Datasheet(HTML) 12 Page - Alliance Semiconductor Corporation

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AS9C25512M2018L
AS9C25256M2018L
9/24/04, v.1.2
Alliance Semiconductor
P. 12 of 30
®
AC timing characteristics[1,2,5,6] (VDD = 2.5 ± 100mV)
Notes:
1. All timings are same for both ports.
2. These values are valid for either level of VDDQ (2.5V/3.3V)
3. A particular port will operate in Pipeline output mode if PL/FT = VDD and in flow-through output mode if PL/FT = 0V. Each port can independently operate in any of these
modes.
4. Output Enable (OE) is an asynchronous input.
5. PL/FT and OPT should be treated as DC signals and should reach steady state before normal operation.
6. Refer AC Test Conditions to view the test conditions used for these measurements.
7. This parameter has to be taken care to avoid collision during simultaneous memory access of the same location.
8. To avoid bus contention, at a given voltage and temperature tLZC is more than tHZC (True in both Pipeline and flow-through output mode).
Parameter
Symbol
-250
-200
-166
-133
Unit Notes
Min. Max. Min.
Max. Min.
Max. Min. Max.
Clock
Cycle Time (Pipeline)
tCYCP
4
-
5
-
6
-
7.5
-
ns
3
Clock High Pulse Width (Pipeline)
tCHP
1.7
-
2
-
2.4
-
3
-
ns
3
Clock Low Pulse Width (Pipeline)
tCLP
1.7
-
2
-
2.4
-
3
-
ns
3
Cycle Time (Flow-Through)
tCYCF
6.5
-
7.5
-
10
-
12
-
ns
3
Clock High Pulse Width (Flow-Through)
tCHF
1.7
-
2
-
2.4
-
3
-
ns
3
Clock Low Pulse Width (Flow-Through)
tCLF
1.7
-
2
-
2.4
-
3
-
ns
3
Output
Clock access time (Pipeline)
tCDP
-
2.8
-
3.4
-
3.6
-
4.2
ns
3
Output Data Hold from Clock High (Pipeline)
tOHP
1
-
1
-
1
-
1
-
ns
Clock High to Output Low-Z (Pipeline)
tLZCP
1
-
1
-
1
-
1
-
ns
3,8
Clock High to Output High-Z (Pipeline)
tHZCP
12.8
1
3.413.6
14.2
ns
3,8
Clock access time (Flow-Through)
tCDF
-
6.5
-
7.5
-
10
-
12
ns
3
Output Data Hold from Clock High (Flow-Through)
tOHF
1
-
1
-
1
-
1
-
ns
Clock High to Output Low-Z (Flow-Through)
tLZCF
1
-
1
-
1
-
1
-
ns
3,8
Clock High to Output High-Z (Flow-Through)
tHZCF
12.8
1
3.413.6
14.2
ns
3,8
Output Enable to Data Valid
tOE
-
2.8
-
3.4
-
3.6
-
4.2
ns
4
Output Enable Low to Output Low-Z
tLZOE
1
-
1
-
1
-
1
-
ns
4
Output Enable High to Output High-Z
tHZOE
12.8
1
3.413.6
14.2
ns
4
Setup
Address Setup to Clock High
tAS
1.2
-
1.5
-
1.7
-
1.8
-
ns
Chip Enable Setup to Clock High
tCES
1.2
-
1.5
-
1.7
-
1.8
-
ns
Byte Enable Setup to Clock High
tBS
1.2
-
1.5
-
1.7
-
1.8
-
ns
R/W
Setup to Clock High
tWS
1.2
-
1.5
-
1.7
-
1.8
-
ns
Input Data Setup to Clock High
tDS
1.2
-
1.5
-
1.7
1.8
-
ns
ADS
Setup to Clock High
tADSS
1.2
-
1.5
-
1.7
-
1.8
-
ns
INC
Setup to Clock High
tINCS
1.2
-
1.5
-
1.7
-
1.8
-
ns
RPT
Setup to Clock High
tRPTS
1.2
-
1.5
-
1.7
-
1.8
-
ns
Hold
Address Hold from Clock High
tAH
0.3
-
0.5
-
0.5
-
0.5
-
ns
Chip Enable Hold from Clock High
tCEH
0.3
-
0.5
-
0.5
-
0.5
-
ns
Byte Enable Hold from Clock High
tBH
0.3
-
0.5
-
0.5
-
0.5
-
ns
R/W
Hold from Clock High
tWH
0.3
-
0.5
-
0.5
-
0.5
-
ns
Input Data Hold from Clock High
tDH
0.3
-
0.5
-
0.5
-
0.5
-
ns
ADS
Hold from Clock High
tADSH
0.3
-
0.5
-
0.5
-
0.5
-
ns
INC
Hold from Clock High
tINCH
0.3
-
0.5
-
0.5
-
0.5
-
ns
RPT
Hold from Clock High
tRPTH
0.3
-
0.5
-
0.5
-
0.5
-
ns
Flag
Interrupt Flag Set Time
tSINT
-
6
-
6
-
6
-
7ns
Interrupt Flag Reset Time
tRINT
-
6
-
6
-
6
-
7ns
Collision Flag Set Time
tSCOL
-
2.8
-
3.4
-
3.6
-
4.2
ns
Collision Flag Reset Time
tRCOL
-
2.8
-
3.4
-
3.6
-
4.2
ns
Port-to-Port Delay
Clock-to-Clock Delay
tCCO
3.0
-
3.5
-
4
-
5
-
ns
7



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