AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 23 of 30

®

IEEE 1149.1 Serial boundary scan (JTAG)

The SRAM incorporates a serial boundary scan Test Access Port (TAP). All JTAG pins operate using JEDEC standard 2.5V I/O logic levels.

In order to operate the device without using the JTAG feature, all JTAG pins may be left unconnected. On power-up, the device will start in

a reset state which will not interfere with normal device operation.

TAP Controller block diagram

Note:

1. x = 111

JTAG timing waveform

Selection

Circuitry

Selection

Circuitry

31 30 29

0

1

2

.

.

.

Identification Register

Bypass Register

Instruction Register

0

1

2

0

1

2

0

.. . . .

TDI

TMS

TCK

TDO

TAP Controller

3

TEST CLK

TRST

TCK

TMS/TDI

TDO

Don’t care

Undefined