B1

DIR

5

7

A1

2

B2

6

A2

3

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC2T45

SCES516K – DECEMBER 2003 – REVISED JUNE 2017

SN74LVC2T45 Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage

Translation

1

1 Features

1

•

Fully Configurable Dual-Rail Design Allows Each

Port to Operate Over the Full 1.65-V to 5.5-V

Power-Supply Range

•

GND, Both Ports Are in the High-Impedance State

•

•

•

Available in the Texas Instruments NanoFree™

Package

•

±24-mA Output Drive at 3.3 V

•

•

Max Data Rates

–

420 Mbps (3.3-V to 5-V Translation)

–

210 Mbps (Translate to 3.3 V)

–

140 Mbps (Translate to 2.5 V)

–

75 Mbps (Translate to 1.8 V)

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

ESD Protection Exceeds JESD 22

–

4000-V Human-Body Model (A114-A)

–

200-V Machine Model (A115-A)

–

1000-V Charged-Device Model (C101)

2 Applications

•

Personal Electronic

•

Industrial

•

Enterprise

•

Telecom

3 Description

This dual-bit noninverting bus transceiver uses two

separate configurable power-supply rails. The A port

voltage from 1.65 V to 5.5 V. The B port is designed

1.65 V to 5.5 V. This allows for universal low-voltage

bidirectional translation between any of the 1.8-V,

2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC2T45 is designed for asynchronous

communication between two data buses. The logic

levels of the direction-control (DIR) input activate

either the B-port outputs or the A-port outputs. The

device transmits data from the A bus to the B bus

when the B-port outputs are activated, and from the B

bus to the A bus when the A-port outputs are

activated. The input circuitry on both A and B ports

always is active and must have a logic HIGH or LOW

The SN74LVC2T45 is designed so that the DIR input

specified for partial-power-down applications using

damaging current backflow through the device when

it is powered down.

input is at GND, both ports are in the high-impedance

state. NanoFree™ package technology is a major

breakthrough in IC packaging concepts, using the die

as the package.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

SN74LVC2T45DCT

SM8 (8)

2.95 mm x 2.80 mm

SN74LVC2T45DCU

VSSOP (8)

2.30 mm x 2.00 mm

SN74LVC2T45YZP

DSBGA (8)

1.89 mm x 0.89 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Functional Block Diagram