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EKTF6708 Datasheet(PDF) 95 Page - ELAN Microelectronics Corp |
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EKTF6708 Datasheet(HTML) 95 Page - ELAN Microelectronics Corp |
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95 / 158 page  eKTF6708 8-Bit Microcontroller IC Product Specification (V1.2) 03.12.2020 85 (This specification is subject to change without prior notice) 6.5 Interrupt The eKTF6708 has 23 interrupts (External, Internal) as listed below: Interrupt Source Enable Condition Int. Flag Int. Vector Priority Internal / External Reset - - 0 High 0 External INT ENI + EXIE=1 EXSF 2 1 External Pin change ENI +ICIE=1 ICSF 4 2 Internal TCC ENI + TCIE=1 TCSF 6 3 Internal LVD ENI+LVDEN & LVDIE=1 LVDSF 8 4 Internal SPI ENI + SPIIE=1 SPISF C 5 Internal AD ENI + ADIE=1 ADSF 10 6 Internal TC1 ENI + TC1IE=1 TC1SF 12 7 Internal PWMPA ENI+PWMAPIE=1 PWMAPSF 14 8 Internal PWMDA ENI+PWMADIE=1 PWMADSF 16 9 Internal I2C Transmit ENI+ I2CTIE I2CTSF 1A 10 Internal I2C Receive ENI+ I2CRIE I2CRSF 1C 11 Internal I2CSTOP ENI+ I2CSTPIE I2CSTPSF 1E 12 Internal PWMPB ENI+PWMBPIE=1 PWMBPSF 24 13 Internal PWMDB ENI+PWMBDIE=1 PWMBDSF 26 14 Internal PWMPC ENI+PWMCPIE=1 PWMCPSF 2A 15 Internal PWMDC ENI+PWMCDIE=1 PWMCDSF 2C 16 Internal UART Receive error ENI+UERRIE=1 UERRSF 2E 17 Internal UART Receive ENI + URIE=1 URSF 30 18 Internal UART Transmit ENI + UTIE=1 UTSF 32 19 Internal System hold ENI+SHIE=1 SHSF 3A 20 Internal Touch Key ENI+TKIE=1 TKSF 3C 21 Internal Touch Key error ENI+TKERRIE=1 TKPESF TKOESF 3E 22 Internal Touch Key Idle with scan ENI+TKCIE=1 TKCSF TKTOSF 40 23 Bank 0 R14~R19 are the interrupt status registers that record the interrupt requests in the relative flags/bits. Bank0 R1B~R20 are the interrupt Mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the enabled interrupts occurs, the next instruction will be fetched from individual address. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts. The flag (except ICSF bit which is set to “0”) in the Interrupt Status Register is set regardless of the status of its mask bit or the execution of ENI. The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). External interrupt is equipped with digital noise rejection circuit (input pulse of less than 4 System Clock Time is eliminated as noise). When an interrupt (Falling edge) is generated by the External interrupt (if enabled), the next instruction will be fetched from Address 002H. Before the interrupt subroutine is executed, the contents of ACC and the R3 (Bit 0~Bit 6) and R4 registers are saved by hardware. If another interrupt occurs, the ACC, R3 |
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