EKTF6708 datasheet(99/158 Pages) EMC

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eKTF6708

8-Bit Microcontroller

IC Product Specification (V1.2) 03.12.2020

 89

(This specification is subject to change without prior notice)

The AD Conversion is considered completed as determined by:

The ADRUN bit of the Bank 0-R3E register is cleared to “0”.

The ADSF bit of the Bank 0-R14 register is set to “1”.

The ADWK bit of the Bank 0-R10 register is set to “1”. Wakes up from ADC

conversion (where it remains in operation during sleep mode).

Wake up and execution of the next instruction if the ADIE bit of the Bank 0-R1B

is enabled and the “DISI” instruction is executed.

Wake up and enter into Interrupt vector if the ADIE bit of Bank 0-R1B is enabled

and the “ENI” instruction is executed.

Enter into an Interrupt vector if the ADIE bit of the Bank 0-R1B is enabled and the

“ENI” instruction is executed.

The results are fed into the ADDL and ADDH registers when the conversion is completed.

If the ADWK is enabled, the device will wake up. Otherwise, the AD conversion will be shut

off, no matter what the status of the ADPD bit is.

6.6.5 Programming Process/Considerations

Follow these steps to obtain data from the ADC:

Write to the 2 bits (ADE1~0) on the Bank 0-R41(ADER1) register to define the

characteristics of P70~P71 (digital I/O, analog channels, or voltage reference

pin)

Write to the Bank 0-R3E~R41 register to configure the AD module:

a) Select the ADC input channel (ADIS1~0)

b) Define the AD conversion clock rate (CKR2~0)

c) Select the VREFS input source of the ADC

d) Set the ADP bit to “1” to begin sampling

Set the ADWK bit, if the wake-up function is employed

Set the ADIE bit, if the interrupt function is employed

Write “ENI” instruction, if the interrupt function is employed

Set the ADRUN bit to “1”

Write “SLEP” instruction or Polling.

Wait for either Wake-up or for the ADRUN bit to be cleared to “0” , and the Status

flag (ADSF) is set “1”, or ADC interrupt occurs.

Read the ADDL and ADDH conversion data registers. If the ADC input channel

changes at this time, the ADDL and ADDH values can be cleared to “0”.

10.

Clear the status flag (ADSF).

11.

For next conversion, go to Step 1 or Step 2 as required. At least two TAD are

required before the next acquisition starts. On the other hand, the timing setting

ADRUN = 1 must be later than the timing setting ADPD=1, and the difference

between the two timings is also two TAD.

EKTF6708 Datasheet(PDF) 99 Page - ELAN Microelectronics Corp

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