Bus Blaster v4 uses the 'H' version of the chip, the latest 3.3volt revision that supports JTAG adaptive

clocking. The circuit is based on a reference design from the FT2232H datasheet.

◾ See the FT2232H breakout board documentation for a complete explanation of the FT2232H

reference circuit

Buffered interface

The buffer translates voltage levels between the FT2232H (3.3volts) and a JTAG device

(1.5volts-3.3volts). The four main JTAG IO pins (TDI, TDO, TCK, TMS) are fixed on the FT2232, but

the other reset and control pins vary among programmers.

Bus Blaster v4 is buffered by a programmable logic chip (CPLD) that can be updated to imitate many

common buffer types. The CPLD programming pins are connected to the secondary JTAG interface on

the FT2232, so uploading a new buffer type is done entirely from software over USB.

Reprogramming logic

Bus Blaster v4 was designed primarily to support the SWV feature of advanced Cortex microcontroller

debugging. Basically the microcontroller has an extra serial UART channel to send debug or other info

back to the programmer. This is implemented by using the second JTAG engine of the FT2232 as a

serial UART input and passing the info to the user through a serial terminal or whatever.

The Bus Blaster v2/v3 used the secondary JTAG block to program the CPLD with different buffer

interfaces. These pins cannot be recycled for use with SWV in the v2/v3 hardware. In v4 we use two

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