NCP5331 datasheet(21/38 Pages) ONSEMI

21 / 38 page

NCP5331

http://onsemi.com

0.25 V and “timing out” at 3 V. The current delivered to the

CPGD capacitor (IPGD) is a function of the ROSC resistor

according to the following equation.

IPGD + 0.52 V ROSC

The programmed delay time can be calculated from

tPGD + CPGD @ (PGDTHRESH * PGDMIN) IPGD

+ CPGD @ (3.0 V * 0.25 V) IPGD

The programmable timer may be disabled (set to 0) by

connecting the CPGD pin to 5 VREF. This will set the PGD

delay time to the internal delay of 200

µs. Figure 26

demonstrates the use of the programmable PGD timer (set

to 6.0 ms) to allow PGD to transition high when VCORE is

safely within the regulation limits for the processor (DAC

±50 mV).

Implementing an Enable Function

An Enable function may be implemented on the NCP5331

in one of two ways. The first method (Method A in

Figure 27) is to pull low on the Ilim pin. This method is the

preferred method, as both the GHx and the GLx pins will be

kept low at turn-off, preventing VCORE from being pulled

below ground.

However, if using the “Timed Hiccup Mode Current

Limit” feature with Method A, the Covc pin will time out

when the Ilim pin is pulled low, and the NCP5331 will not

turn back on (after time out) unless the power is recycled.

This can be avoided by adding another transistor to the Covc

pin, thereby keeping it low while the part is disabled.

The second method (Method B in Figure 28) is to pull low

on the NCP5331’s comp pin. With this method, GHx will be

low and GLx will be high while the part is disabled.

However, under Method B, if the part is disabled at

turn-on, and if using the “Timed Hiccup Mode Current

Limit” feature, the Covc pin will again time out and the

NCP5331 will not be able to be turned on after the time out

has occurred. This too can be avoided by the use of a

transistor at the Covc pin keeping it low while the part is

disabled.

If using Method B but not with a transistor at the Covc pin,

a 1.0 K resistor must be added between the drain of the

transistor and the Comp pin to prevent the current limit from

being tripped when the Comp pin is quickly pulled low.

ILIM

Figure 27. Enable Method A

*Needed if using ‘Timed

Hiccup Mode Current Limit’

QILIM

BSS123

COVC

*QCOVC

BSS123

Hi to Disable

Lo to Enable

COMP

Figure 28. Enable Method B

QCOMP

BSS123

COVC

**QCOVC

BSS123

Hi to Disable

Lo to Enable

1.0 k

*Needed if not using QCovc

**Allows Disabling at Turn-On

(when using ‘Timed Hiccup Mode Current Limit’)

NCP5331 Datasheet(PDF) 21 Page - ON Semiconductor

NCP5331 Datasheet(HTML) 21 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL