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ADSC573WCBCZ3XX Datasheet(PDF) 84 Page - Analog Devices

Part # ADSC573WCBCZ3XX
Description  SHARC Dual-Core DSP with ARM Cortex-A5
PDF  142 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSC573WCBCZ3XX Datasheet(HTML) 84 Page - Analog Devices

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 84 / 142 page
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Rev. B
|
Page 84 of 142
|
June 2018
ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573
Table 55. LPs—Transmit1
Parameter
Min
Max
Unit
Timing Requirements
tSLACH
LPx_ACK Setup Before LPx_CLK Low
2 × tSCLK0 + 13.5
ns
tHLACH
LPx_ACK Hold After LPx_CLK Low
–5.5
ns
Switching Characteristics
tDLDCH
Data Delay After LPx_CLK High
2.23
ns
tHLDCH
Data Hold After LPx_CLK High
–2.3
ns
tLCLKTWL
2
LPx_CLK Width Low
0.4 × tLCLKTPROG
0.6 × tLCLKTPROG
ns
tLCLKTWH
2
LPx_CLK Width High
0.4 × tLCLKTPROG
0.6 × tLCLKTPROG
ns
tLCLKTW
2
LPx_CLK Period
N × tLCLKTPROG – 0.6
ns
tDLACLK
LPx_CLK Low Delay After LPx_ACK High
tSCLK0 + 4
2 × tSCLK0 + 1 × tLPCLK + 10
ns
1 Specifications apply to LP0 and LP1.
2 See Table 27 for details on the minimum period that can be programmed for tLCLKTPROG.
Figure 29. LPs—Transmit
LPx_CLK
LPx_Dx
(DATA)
LPx_ACK (IN)
OUT
tDLDCH
tHLDCH
tSLACH
tHLACH
tDLACLK
tLCLKTWH
tLCLKTWL
LAST BYTE
TRANSMITTED
FIRST BYTE
TRANSMITTED
1
NOTES
The t
SLACH and tHLACH
specifications apply only to the LPx_CLK falling edge. If these specifications are met,
LPx_CLK extends and the dotted LPx_CLK falling edge does not occur as shown. The position of the
dotted falling edge can be calculated using the t
LCLKTWH specification.
t
LCLKTWH Min must be used for tSLACH
and t
LCLKTWH Max for tHLACH.



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