DM8108
8 port 10/100M Fast Ethernet Switching Controller
Preliminary
9
Version: DM8108-DS-P02
November 25, 1999
99 – 96
RXD5(3:0)
I
Receive data for port 5; synchronous to RXCLK5.
115 - 112
RXD6(3:0)
I
Receive data for port 6; synchronous to RXCLK6.
137 - 128
RXD7(3:0)
I
Receive data for port 7; synchronous to RXCLK7.
127,111,95,79,
60,44,28,12
RXCLK(7:0)
I
Receive clock for port 7 – 0; synchronous to RXD, RXDV,RXER; has
same clock rate as TXCLK.
124,108,92,76,
57,41,25,9
RXDV(7:0)
I
Receive data valid indication for port 7 – 0.
123,107,91,75,
56,40,24,8
RXER(7:0)
I
Receive data error indication for port 7 – 0.
126,110,94,78,
59,43,27,11
CRS(7:0)
I
Carrier sense; active high. Indicates that either the transmit or
receive medium is not Idle. CRS is not synchronous to any clock.
125,109,93,77,
58,42,26,10
COL(7:0)
I
Collision Detect; active high. Indicates a collision has been detected
on the wire.
This input is ignored during full duplex operation and in the half duplex
mode while TXEN of the same port is low.
72
MDCLK
I/O
Serial MII management interface clock signal: 1MHz clock for MDIO
data reference. Connected to all PHY ports; It is an input pin if the
device # is not 0 in SDRAM mode; else, it is an output pin.
73
MDIO
I/O
Serial MII management interface data; this bi-direction line is used to
transfer control Information and status between the PHY and the
DM8108. It conforms to the IEEE-802.3 specifications.
This signal may be connected to the PHY devices of all ports.
Pulled down if not used.
Miscellaneous Interface pins
Pin No.
Pin Name
I/O
Description
175
SCLK
I
Memory clock: used by the DRAM state machine.
5
RST*
I
Reset signal for the chip.
6
TESTEN*
I
Test pin to enable test functions
Power pins
Pin No.
Pin Name
I/O
Description
23,55,90,122,
156,185,198
VCC
Power
Connected to 3.3V Power plane
1,7,39,71,74,
106,138,147,
165,174,176,
181,190,196,
203
GND
Ground
Connected to Ground plane
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