TDA5340 datasheet(32/63 Pages) INFINEON

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TDA5340

SmartLEWISTM TRX

Functional Overview

Data Sheet

Revision 1.2, 13.06.2012

Clock Recovery is implemented as standard ADPLL PI regulator with Timing Extrapolation Unit for fast settling. In

the unlocked state, the Timing Extrapolation Unit calculates the frequency offset for the incoming data stream. If

the defined number of Bi-phase encoded bits are detected (the RUNIN length can be set in the x_CDRRI register),

the I-part and the PLL oscillator will be set and the PLL will be locked. When x_CDRRI.RUNLEN is set to small

values, then the I-part is less accurate (residual error) and can lead to a longer needed PLL settling time and worse

performance in the first following bits. Therefore the selected default value is a good compromise between fast

symbol synchronization and accuracy/performance. Duty cycle and data rate acceptance limits are adjustable via

registers. After locking, the clock must be stable and must follow the reference input. Therefore, a rapid settling

procedure (Timing Extrapolation Unit) and a slow PLL are implemented. If the PLL is locked, the reference signal

from the Clock Recovery Slicer is used in the phase detector block to compute the actual error. The error is used

in the PI loop filter to set the digital controlled oscillator running frequency. For the P, I and Timing Extrapolation

Unit settings, the default values for the x_CDRP and x_CDRI control registers are recommended.The PLL will be

unlocked, if a code violation of more than the defined length is detected, which is set in the x_TVWIN control

The PLL oscillator generates the chip clock frequency is equal to 2 times the data rate.

2.6.8.7

Wake-Up Generator

A wake-up generation unit is used only in the Self Polling Mode for the detection of a predefined wake-up criterion

in the received pattern. There are two groups of configurable wake-up criteria:

•

Wake-up on Level criteria

•

Wake-up on Data criteria

The search for the wake-up data criterion is started if data chip synchronization has occurred within the predefined

number of symbols, otherwise the wake-up search is aborted. Several different wake-up patterns, like random bit,

equal bit, bit pattern or bit synchronization, are programmable.Additional level criterion fulfilment for RSSI or Signal

Recognition can lead to a fast wake-up and to a change to Run Mode Self Polling. Whenever one of these Wake-

up Level criteria is enabled and exceeds a programmable threshold, a wake-up has been detected.The Wake-up

Level criterion can be used very effectively in combination with the Ultrafast Fall Back to SLEEP Mode for further

decreasing the needed active time of the autonomous receive mode. A configurable observation time for Wake-

up on Level can be set in the x_WULOT register.

2.6.8.8

Frame Synchronization

The Frame Synchronization Unit (Framer) synchronizes to a specific pattern to identify the exact start of a payload

data frame within the data stream. This pattern is called Telegram Start Identifier (TSI).There are different TSI

modes selectable via the configuration:

•

16-Bit TSI Mode, supporting a TSI length of up to 16 bits or 32 chips

•

8-Bit Parallel TSI Mode, supporting two independent TSI pattern of up to 8 bits length each. Different payload

length is possible for these two TSI pattern.

•

8-Bit Extended TSI Mode, identical to 8-Bit Parallel TSI Mode, but identifies which pattern matches by adding

a single bit at the beginning of the data frame

•

8-Bit TSI Gap Mode, supporting two independent TSI pattern separated by a discontinuity

All SFRs configuring the Frame Synchronization Unit support the Multi-Configuration capability (Config A, B, C

and D). The Framer starts working in Run Mode Slave after Symbol Sync found and in Self Polling Mode after

wake-up found and searches for a frame until TSI is found or synchronization is lost. The input of the Framer is a

sequence of Bi-phase encoded data (chips). Basically the Framer consists of two identical correlators of 16 chips

in length. It allows a Telegram Start Identifier (TSI) to be composed of Bi-phase encoded “Zeros” and “Ones”. The

active length of each of the 16 chips correlators is defined independently in the x_TSILENA and x_TSILENB

registers. The pattern to match is defined as a sequence of chips in the x_TSIPTA0, x_TSIPTA1, x_TSIPTB0 and

x_TSIPTB1 registers.

TDA5340 Datasheet(PDF) 32 Page - Infineon Technologies AG

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