TDA5340 datasheet(21/63 Pages) INFINEON

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TDA5340

SmartLEWISTM TRX

Functional Overview

Data Sheet

Revision 1.2, 13.06.2012

feeds a digital FSK demodulator. This block demodulates the FSK data and delivers an AFC signal which controls

the divider factor of the PLL synthesizer. A digital receiver, which comprises RSSI peak detectors, a matched data

filter, a clock and data recovery, a data slicer, a frame synchronization and a data FIFO, decodes the received

ASK or FSK data stream. The recovered data and clock signals are accessible via 2 separate pins. The FIFO data

buffer is accessible via the SPI bus interface.The crystal oscillator serves as the reference frequency for the PLL

phase detector, the clock signal of the Sigma-Delta modulator and divided by two as the 2nd local oscillator signal.

To accelerate the start up of the crystal oscillator two modes are selectable: a Low Power Mode (with lower

precision) and a High Precision Mode.

2.4

Block Overview

The TDA5340 is separated into the following main blocks:

•

RF / IF Receiver

•

Power Amplifier

•

Crystal Oscillator and Clock Divider

•

Sigma-Delta Fractional-N PLL Synthesizer

•

ASK / FSK Demodulator incl. AFC and AGC

•

RSSI Peak Detector

•

Digital Baseband Receiver

•

Digital Baseband Transmitter

•

Power Supply Circuitry

•

System Interface

•

System Management Unit

TDA5340 Datasheet(PDF) 21 Page - Infineon Technologies AG