Feature Descriptions

OUTPUT CHARACTERISTICS

The output characteristics of the SCAN90004 have been

optimized for point-to-point backplane and cable applica-

tions, and are not intended for multipoint or multidrop signal-

ing.

POWERDOWN MODE

The PWDN input activates a hardware powerdown mode.

When the powerdown mode is active (PWDN=L), all input

and output buffers and internal bias circuitry are powered off

and disabled. Outputs are tri-stated in powerdown mode.

JTAG Circuitry is active per the IEEE standard, but does not

switch unless TCK is toggling. When exiting powerdown

mode, there is a delay associated with turning on bandgap

references and input/output buffer circuits as indicated in the

LVDS Output Switching Characteristics

PRE-EMPHASIS

Pre-emphasis dramatically reduces ISI jitter from long or

lossy transmission media. Two pins are used to select the

pre-emphasis level for all outputs: off, low, medium, or high.

Pre-emphasis Control Selection Table

PEM1

PEM0

Pre-Emphasis

0

0

Off

0

1

Low

1

0

Medium

1

1

High

INPUT FAILSAFE BIASING

External pull up and pull down resistors may be used to

provide enough of an offset to enable an input failsafe under

open-circuit conditions. This configuration ties the positive

LVDS input pin to V

LVDS input pin is tied to GND by a pull down resistor. The

pull up and pull down resistors should be in the 5k

Ω to 15kΩ

range to minimize loading and waveform distortion to the

driver. The common-mode bias point ideally should be set to

approximately 1.2V (less than 1.75V) to be compatible with

the internal circuitry. Please refer to application note AN-

1194 “Failsafe Biasing of LVDS Interfaces” for more informa-

tion.

Design-for-Test (DfT) Features

IEEE 1149.1 (JTAG) SUPPORT

The SCAN90004 supports a fully compliant IEEE 1149.1

interface. The Test Access Port (TAP) provides access to

boundary scan cells at each LVTTL I/O on the device for

interconnect testing. Differential pins are included in the

same boundary scan chain but instead contain IEEE1149.6

cells. IEEE1149.6 is the improved IEEE standard for testing

high-speed differential signals.

Refer to the BSDL file located on National’s website for the

details of the SCAN90004 IEEE 1149.1 implementation.

IEEE 1149.6 SUPPORT

AC-coupled differential interconnections on very high speed

(1+ Gbps) data paths are not testable using traditional IEEE

1149.1 techniques. The IEEE 1149.1 structures and meth-

ods are intended to test static (DC-coupled), single ended

networks. IEEE1149.6 is specifically designed for testing

high-speed differential, including AC coupled networks.

The SCAN90004 is intended for high-speed signalling up to

1.5 Gbps and includes IEEE1149.6 on all differential inputs

and outputs.

FAULT INSERTION

Fault Insertion is a technique used to assist in the verification

and debug of diagnostic software. During system testing

faults are "injected" to simulate hardware failure and thus

help verify the monitoring software can detect and diagnose

these faults. In the SCAN90004 an IEEE1149.1 "stuck-at"

instruction can create a stuck-at condition, either high or low,

on any pin or combination of pins. A more detailed descrip-

tion of the stuck-at feature can be found in NSC Applications

note AN-1313.

www.national.com

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