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STM32L552CCT3PTR Datasheet(PDF) 278 Page - STMicroelectronics |
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STM32L552CCT3PTR Datasheet(HTML) 278 Page - STMicroelectronics |
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278 / 340 page  Electrical characteristics STM32L552xx 278/340 DS12737 Rev 6 Figure 53. USART master mode timing diagram tsu(NSS) NSS setup time Slave mode Tker +4 - - - th(NSS) NSS hold time Slave mode 1 - - tw(SCKH) tw(SCKL) SCK high and low time Master mode 1/fsck/2-1 1/fsck/2 1/fsck/2+1 tsu(MI) Data input setup time Master mode 22.5 - - ns tsu(SI) Slave mode 1 - - th(MI) Data input hold time Master mode 0 - - th(SI) Slave mode 3 - - tv(SO) Data output valid time Slave mode 2.7<VDD<3.6V -14.5 19 Slave mode 1.71<VDD<3.6V -14.5 26 tv(MO) Master mode - 1.5 3 th(SO) Data output hold time Slave mode 1.71<VDD<3.6V 12 - - th(MO) Master mode 1 - - 1. Guaranteed by characterization results, not tested in production. Table 131. USART characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit MSv64015V1 CPHA=0 TX RX CPHA=0 MSB MSB CPOL=0 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(RX) CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(RX) tv(TX) th(TX) LSB LSB |
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