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ZSSC3154BA3R Datasheet(PDF) 16 Page - Renesas Technology Corp |
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ZSSC3154BA3R Datasheet(HTML) 16 Page - Renesas Technology Corp |
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16 / 29 page ![]() ZSSC3154 Datasheet © 2016 Integrated Device Technology, Inc. 16 January 22, 2016 2.8 Analog Front End The analog front-end (AFE) consists of the multiplexer (MUX), the programmable gain amplifier (PGA), and the analog-to-digital converter (ADC). 2.8.1 Programmable Gain Amplifier Table 2.1 shows the adjustable gains, the corresponding sensor signal input spans, and the common mode range limits. Table 2.1 Adjustable Gains and Resulting Sensor Signal Spans and Common Mode Ranges PGA Gain aIN Maximum Input Span VIN_SPAN [mV/V] 1) Input Common Mode Range VIN_CM [% VDDA] 2) XZC = Off XZC = On 420 1.8 29 to 65 45 to 55 280 2.7 29 to 65 45 to 55 210 3.6 29 to 65 45 to 55 140 5.4 29 to 65 45 to 55 105 7.1 29 to 65 45 to 55 70 10.7 29 to 65 45 to 55 52.5 14.3 29 to 65 45 to 55 35 21.4 29 to 65 45 to 55 26.3 28.5 29 to 65 45 to 55 14 53.75 29 to 65 45 to 55 9.3 80 29 to 65 45 to 55 7 107 29 to 65 45 to 55 2.8 267 32 to 57 Not applicable 1) Recommended maximum internal signal range is 80% of supply voltage. Span is calculated by the following formula: VIN_SPAN = 0.8 (VVBR_T – VVBR_B) / aIN. 2) Refer to section 2.8.2 for an explanation of the analog offset compensation. Recommendation: To achieve the best stability and linearity performance of the AFE, operate the PGA in a voltage range within 10% to 90% of the ratiometric reference voltage VREF = (VVBR_T – VVBR_B). The gain must be selected to guarantee this constraint for the entire operating temperature range of the application and for the specified sensor bridge tolerances. |
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