VD6640 datasheet(66/126 Pages) STMICROELECTRONICS

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Video data interface

VG6640, VD6640

66/126

DocID023597 Rev 11

Video data interface

The video data stream is output from the image sensor through either the camera serial

interface (CSI-2) or the parallel ITU interface. Both interfaces can transmit video data and

other auxiliary information.

5.1

MIPI CSI-2 serial data link

Image data may be transferred to the companion device through a dual-lane MIPI CSI-2

serial interface. The CSI-2 interface is capable of transmitting at up to 528 Mbit/s per lane.

Full resolution images (in 22:12-bit compressed format) may be transferred at up to 45 fps

and 720p resolution images at up to 60 fps.

The CSI-2 interface is low EMI and more suitable for use over longer transmission distances

when compared with the parallel interface. The CSI-2 interface is suitable for use in

potentially noisy environments.

For full details of the MIPI CSI-2 interface, refer to the MIPI Alliance Standard for Camera

Serial Interface (CSI-2) - Version 1.00.

5.1.1

Features

The image sensor is MIPI CSI-2 D-PHY v1.1 compliant.

The CSI-2 clock and data lane transmitters support:

•

unidirectional master

•

HS-TX, high speed transmit

•

LP-TX, low power transmit

•

CIL-MUYN function (data transmitter only)

•

CIL-MCNN function (clock transmitter only)

Physical layer

The physical layer (D-PHY) of the CSI-2 interface is based on LVDS signalling, resulting in

reduced EMI and excellent EMC, suitable for use in potentially noisy environments. Data

and clock signals are transmitted over balanced 100

Ω differential-impedance transmission

lines.

The CSI-2 MIPI D-PHY physical layer comprises of:

•

one clock lane and two data lanes

•

unidirectional clock lane supporting ultra low power mode (ULPM)

•

unidirectional data lane supporting ULPM (using forward escape mode)

•

power on/off and reset sequences are defined as transitions to/from ULPM

The CSI-2 interface may be configured as single or dual lane. The data lanes may be

swapped if required. Similarly, the sense of a data lane may be switched. The slew rate of

the clock and data lanes is configurable. The CSI-2 interface will remain in a high

impedance state if the parallel interface has been selected as the output interface.

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