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VSC8221HH Datasheet(PDF) 69 Page - Microsemi Corporation |
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VSC8221HH Datasheet(HTML) 69 Page - Microsemi Corporation |
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69 / 138 page  VSC8221 Data Sheet VMDS-10106 Revision 4.1 December 2006 69 of 106 106 23.2.2 Register 1 (01h) – Mode Status Register 1.15 – 100BASE-T4 Capability The VSC8221 is not 100BASE-T4 capable, so this bit is hard-wired to “0”. 1.14 – 100BASE-X FDX Capability The VSC8221 is 100BASE-X FDX capable, so this bit is hard-wired to “1”. 1.13 – 100BASE-X HDX Capability The VSC8221 is 100BASE-X HDX capable, so this bit is hard-wired to “1”. 1.12 – 10BASE-T FDX Capability The VSC8221 is 10BASE-T FDX capable, so this bit is hard-wired to “1”. 1.11 – 10BASE-T HDX Capability The VSC8221 is 10BASE-T HDX capable, so this bit is hard-wired to “1”. 1.10 – 100BASE-T2 FDX Capability The VSC8221 is not 100BASE-T2 FDX capable, so this bit is hard-wired to “0”. 1.9 – 100BASE-T2 HDX Capability The VSC8221 is not 100BASE-T2 HDX capable, so this bit is hard-wired to “0”. Register 1 (01h) – Mode Status Register Bit Name Access States Reset Value Sticky 15 100BASE-T4 Capability RO 1 = 100BASE-T4 capable 0 14 100BASE-X FDX Capability RO 1 = 100BASE-X FDX capable 1 13 100BASE-X HDX Capability RO 1 = 100BASE-X HDX capable 1 12 10BASE-T FDX Capability RO 1 = 10BASE-T FDX capable 1 11 10BASE-T HDX Capability RO 1 = 10BASE-T HDX capable 1 10 100BASE-T2 FDX Capability RO 1 = 100BASE-T2 FDX capable 0 9 100BASE-T2 HDX Capability RO 1 = 100BASE-T2 HDX capable 0 8 Extended Status Enable RO 1 = Extended status information present in R15 1 7 Reserved RO 0 6 Preamble Suppression Capability RO 1 = MF preamble may be suppressed 0 = MF preamble always required 1 5 Auto-Negotiation Complete RO 1 = Auto-negotiation complete 0 = Auto-negotiation not complete 0 4 Remote Fault RO LH 1 = Far-end fault detected 0 = No fault detected 0 3 Auto-Negotiation Capability RO 1 = Auto-negotiation capable 1 2 Link Status1 1 The status of this bit remains unchanged when the PHY is put in Power Down mode by setting Mii Register 0.11 or by asserting the TXDiS/SRESET pin. RO LL 1 = Link is up 0 = Link is down 0 1 Jabber Detect RO LH 1 = Jabber condition detected 0 = No jabber condition detected 0 0 Extended Capability RO 1 = Extended register capable 1 |
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