ATMEGA640 datasheet(17/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 7-6.

The Parallel Instruction Fetches and Instruction Executions

Figure 7-7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using

two register operands is executed, and the result is stored back to the destination register.

Figure 7-7.

Single Cycle ALU Operation

7.8

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a

separate program vector in the program memory space. All interrupts are assigned individual enable bits which

must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the

interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits

BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 325 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.

The complete list of vectors is shown in “Interrupts” on page 101. The list also determines the priority levels of the

different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next

is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash sec-

tion by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 101 for more

information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the

BOOTRST Fuse, see “Memory Programming” on page 325.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user soft-

ware can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current

interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For

these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt

handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writ-

ing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding

interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

clk

CPU

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