MPC5554 Microcontroller Product Brief, Rev. 2.1

Features

Freescale Semiconductor

8

– Chaining of DSI submodules

– Triggered transfer control and change in data transfer control (for reduced EMI)

•

2 enhanced serial communication interface (eSCI) modules

— UART mode provides NRZ format and half or full duplex interface

— eSCI bit rate up to 1 Mbps

— Advanced error detection, and optional parity generation and detection

— Word length programmable as 8 or 9 bits

— Separately enabled transmitter and receiver

— LIN Support

— DMA support

— Interrupt request support

•3 FlexCANs

— 64 message buffers each

— Full implementation of the CAN protocol specification, Version 2.0B

— Based on and including all existing features of the Freescale TouCAN module

— Programmable acceptance filters

— Short latency time for high priority transmit messages

— Arbitration scheme according to message ID or message buffer number

— Listen only mode capabilities

— Programmable clock source: system clock or oscillator clock

•

Nexus development interface (NDI)

— Per IEEE

®-ISTO 5001-2003

— Real time development support for e200z6 core and eTPU engines through Nexus Class 3

(some Class 4 support)

— Data trace of eDMA accesses

— Read and write access

— Configured via the IEEE

® 1149.1 (JTAG) port

— High bandwidth mode for fast message transmission

— Reduced bandwidth mode for reduced pin usage

•IEEE

® 1149.1 JTAG controller (JTAGC)

—IEEE

® 1149.1-2001 Test Access Port (TAP) interface

— A JCOMP input that provides the ability to share the TAP. Selectable modes of operation

include JTAGC/debug or normal system operation.

— A 5-bit instruction register that supports IEEE

® 1149.1-2001 defined instructions

— A 5-bit instruction register that supports additional public instructions

— 3 test data registers: bypass, boundary scan, and device identification