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SK645/50/SA Datasheet(PDF) 8 Page - ON Semiconductor |
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SK645/50/SA Datasheet(HTML) 8 Page - ON Semiconductor |
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8 / 30 page ![]() SECO−MDK−4KW−65SPM31−GEVB www.onsemi.com 8 FAN8303 and NCP718 Auxiliary Power Supplies The FAN8303 is a non−isolated buck that is used as converter from 15 Vdc to 5 Vdc output. The maximum power demand is 2.9 W. Figure 6 depicts the schematic of the 5 Vdc auxiliary power supply. Similarly to the NCP1063, the design and sizing of the passive components has been inspired by the applications notes in [4]. The desired output voltage value can be set by tuning the values of the voltage divider (R5 and R6) connected to the FB pin. Additionally, the value of C17 on the COMP pin is tuned empirically to reflect the desired voltage at the converter output. The controller operates at fixed 370 kHz with an efficiency up to 90%. This allows a design with only 22 mH magnetizing inductance (see L3) and two 22 mF capacitors (see C13 and C14). Finally, Figure 6 depicts the NCP718 LDO, which is responsible for the 3.3 Vdc rail generation. Figure 6. Schematic of Auxiliary 5 Vdc and 3.3 Vdc Power Supply Inverter Stage: Compact Intelligent Power Module (IPM) Technology This subsection shows how the necessary circuitry for operation, measurement and protection is setup around the NFAM5065L4B IPM. In addition, it illustrates the necessary circuitry to provide and capture the signals around the module (i.e. the output signals: T_MODULE, IPM_FAULT; and the input signals: ITRIP, IPM_DIS, and gate driver signals INH_U, INH_V, INH_W, INL_U, INL_V, INL_W). Finally, it illustrates the provision of the voltage rails for the IPM (15 Vdc rail reference), as well as the measurement of the DC−Link and inverter−phase voltages. Activation of IPM stage (connection to 15 Vdc power supply) is via J1 (soldered pads). Figure 7 shows the J1 pads at the bottom side of the board; mind that pads should be soldered together to enable the 15 Vdc to the IPM. Following, Figure 8 shows the schematic of the inverter stage and the necessary circuitry around it. Finally, Figure 8 depicts the DC−Link voltage (voltage divider containing R46, R52, R53 and R55) and the inverter output phase−voltage measurement circuitry (voltage divider for phase−U containing R31, R34, R40 and R42; voltage divider for phase−V containing R32, R35, R41 and R43; and voltage divider for phase−W containing R29, R33, R39 and R44). The inverter output voltage phases can be used by the software for zero crossing detection or other control purposes. The signals from the 10 m W shunt resistors are going to current measurement and over−current protection circuits. Details regarding the ADC resolution of the above sensed electrical quantities can be found in Table 1. Next paragraphs are dedicated to the elaboration of the above mentioned circuitries. Figure 7. J1 Pads at the Bottom of the Board (the Pads should be Soldered to Enable the 15 Vdc in the IPM) |
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