9.3 Feature Description

Table 9-1 provides an overview of the device features.

Table 9-1. Device Features

PART NUMBER

CHANNEL DIRECTION

MAXIMUM DATA

RATE

DEFAULT

OUTPUT

PACKAGE

RATED ISOLATION(1)

ISOS141-SEP

With F suffix

3 Forward,

1 Reverse

100 Mbps

Low

DBQ-16

(1)

See Section 6.7 for detailed isolation ratings.

9.3.1 Radiation Tolerance

Total Ionizing Dose (TID)— ISOS141-SEP is a radiation tolerant, TI Space Enhanced Plastic (Space EP)

device, and as such it has a Total Ionizing Dose (TID) level specified in the “Device Information” table on the

front page. Testing and qualification of these products is done on a wafer level according to MIL-STD-883,

Test Method 1019. Radiation Lot Acceptance Testing (RLAT) is performed at the 30-krad TID levels. A TID

characterization report is available. Group E TID RLAT data are available with lot shipments as part of the QCI

summary reports.

Single-Event Effects (SEE)— one-time SEE characterization was performed according to EIA/JEDEC

standard, EIA/JEDEC57 to linear energy transfer (LET) = 43 MeV

Latch-Up (SEL) or Single-Event Dielectric Rupture (SEDR) were observed.

15 units was exposed to radiation testing per MILSTD-883, Method 1017 for Neutron Irradiation.

Radiation Testing and Characterization Reports— are available for all radiation effects described in this

section, to find the latest reports go to the ISOS141-SEP Technical Documentation section on TI.com.

9.3.2 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. Although system-level performance

and reliability depends, to a large extent, on the application board design and layout, the ISOS141-SEP device

incorporates many chip-level design improvements for overall system robustness. Some of these improvements

include:

• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.

• Low-resistance connectivity of ESD cells to supply and ground pins.

• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

www.ti.com

ISOS141-SEP

SLLSFN1 – MAY 2021

Copyright © 2021 Texas Instruments Incorporated

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