ADGS1612

Data Sheet

Rev. 0 | Page 14 of 29

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

2

1

3

4

5

6

18

17

16

15

14

13

D4

S4

GND

S1

D1

D3

S3

NIC

S2

D2

ADGS1612

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED PAD IS CONNECTED

INTERNALLY. FOR INCREASED RELIABILITY

OF THE SOLDER JOINTS AND MAXIMUM

THERMAL CAPABILITY, IT IS RECOMMENDED

THAT THE EXPOSED PAD BE SOLDEREDTO

2. NIC = NOT INTERNALLY CONNECTED.

Figure 5. Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

D1

Drain Terminal 1. This pin can be an input or an output.

2

S1

Source Terminal 1. This pin can be an input or an output.

3

Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.

4, 11

GND

Ground (0 V) Reference.

5

S4

Source Terminal 4. This pin can be an input or an output.

6

D4

Drain Terminal 4. This pin can be an input or an output.

7, 8, 10, 12,

16, 19, 24

NIC

Not Internally Connected. These pins are not internally connected.

9

Pull the pin low to complete a hardware reset. All switches are opened, and the appropriate registers are set

to their default settings.

13

D3

Drain Terminal 3. This pin can be an input or an output.

14

S3

Source Terminal 3. This pin can be an input or an output.

15

Most Positive Power Supply Potential.

17

S2

Source Terminal 2. This pin can be an input or an output.

18

D2

Drain Terminal 2. This pin can be an input or an output.

20

SDO

Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or for reading

back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of

21

CS

Active Low Control Input. CS is the frame synchronization signal for the input data. When CS goes low, it

powers on the SCLK buffers and enables the input shift register. Data is transferred in on the falling edges of

the following clocks. Taking CS high updates the switch condition.

22

SCLK

Serial Clock Input. Data is captured on the positive edge of SCLK. Data is transferred at rates of up to 50 MHz.

23

SDI

Serial Data Input. Data is captured on the positive edge of the serial clock input.

EPAD

Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and