AIS2IH datasheet(45/63 Pages) STMICROELECTRONICS

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8.23

INT_DUR (33h)

Interrupt duration register (r/w)

Table 65. INT_DUR register

LATENCY3

LATENCY2

LATENCY1

LATENCY0

QUIET1

QUIET0

SHOCK1

SHOCK0

Table 66. INT_DUR register description

LATENCY[3:0]

Duration of maximum time gap for double-tap recognition. When double-tap recognition is enabled, this

Default value is LATENCY[3:0] = 0000 (which is 16 * 1/ODR)

1 LSB = 32 * 1/ODR

QUIET[1:0]

Expected quiet time after a tap detection: this register represents the time after the first detected tap in which

there must not be any overthreshold event.

Default value is QUIET[1:0] = 00 (which is 2 * 1/ODR)

1 LSB = 4 * 1/ODR

SHOCK[1:0]

Maximum duration of over-threshold event: this register represents the maximum time of an over-threshold

signal detection to be recognized as a tap event.

Default value is SHOCK[1:0] = 00 (which is 4 * 1/ODR)

1 LSB = 8 *1/ODR

8.24

WAKE_UP_THS (34h)

Wakeup threshold register (r/w)

Table 67. WAKE_UP_THS register

SINGLE_

DOUBLE_

TAP

SLEEP_ ON

WK_THS5

WK_THS4

WK_THS3

WK_THS 2

WK_THS 1

WK_THS 0

Table 68. WAKE_UP_THS register description

SINGLE_DOUBLE_ TAP

Enable single/double-tap event. Default value: 0

(0: only single-tap event is enabled; 1: single and double-tap events are enabled)

SLEEP_ON

Sleep (inactivity) enable. Default value: 0

(0: sleep disabled; 1: sleep enabled)

WK_THS[5:0]

Wakeup threshold, 6-bit unsigned 1 LSB = 1/64 of FS. Default value: 000000

AIS2IH

INT_DUR (33h)

DS12421 - Rev 4

page 45/63

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