LSM6DSO32X datasheet(155/162 Pages) STMICROELECTRONICS

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Table 107. MLC_STATUS_MAINPAGE register description .............................................. 70

Table 108. STATUS_MASTER_MAINPAGE register................................................... 71

Table 109. STATUS_MASTER_MAINPAGE register description .......................................... 71

Table 110. FIFO_STATUS1 register .............................................................. 71

Table 111. FIFO_STATUS1 register description ...................................................... 71

Table 112. FIFO_STATUS2 register .............................................................. 72

Table 113. FIFO_STATUS2 register description ...................................................... 72

Table 114. TIMESTAMP output registers .......................................................... 73

Table 115. TIMESTAMP output register description ................................................... 73

Table 116. TAP_CFG0 register ................................................................. 74

Table 117. TAP_CFG0 register description ......................................................... 74

Table 118. TAP_CFG1 register ................................................................. 75

Table 119. TAP_CFG1 register description ......................................................... 75

Table 120. TAP priority decoding ................................................................ 75

Table 121. TAP_CFG2 register ................................................................. 75

Table 122. TAP_CFG2 register description ......................................................... 75

Table 123. TAP_THS_6D register ............................................................... 76

Table 124. TAP_THS_6D register description ....................................................... 76

Table 125. Threshold for D4D/D6D function ........................................................ 76

Table 126. INT_DUR2 register.................................................................. 77

Table 127. INT_DUR2 register description ......................................................... 77

Table 128. WAKE_UP_THS register.............................................................. 77

Table 129. WAKE_UP_THS register description ..................................................... 77

Table 130. WAKE_UP_DUR register ............................................................. 78

Table 131. WAKE_UP_DUR register description ..................................................... 78

Table 132. FREE_FALL register ................................................................ 79

Table 133. FREE_FALL register description ........................................................ 79

Table 134. Threshold for free-fall function .......................................................... 79

Table 135. MD1_CFG register .................................................................. 80

Table 136. MD1_CFG register description.......................................................... 80

Table 137. MD2_CFG register .................................................................. 81

Table 138. MD2_CFG register description.......................................................... 81

Table 139. I3C_BUS_AVB register ............................................................... 82

Table 140. I3C_BUS_AVB register description....................................................... 82

Table 141. INTERNAL_FREQ_FINE register........................................................ 82

Table 142. INTERNAL_FREQ_FINE register description................................................ 82

Table 143. X_OFS_USR register ................................................................ 82

Table 144. X_OFS_USR register description ........................................................ 82

Table 145. Y_OFS_USR register ................................................................ 83

Table 146. Y_OFS_USR register description ........................................................ 83

Table 147. Z_OFS_USR register ................................................................ 83

Table 148. Z_OFS_USR register description ........................................................ 83

Table 149. FIFO_DATA_OUT_TAG register......................................................... 84

Table 150. FIFO_DATA_OUT_TAG register description ................................................ 84

Table 151. FIFO tag ......................................................................... 84

Table 152. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers .................................... 85

Table 153. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description ............................ 85

Table 154. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers .................................... 85

Table 155. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description ............................ 85

Table 156. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers .................................... 85

Table 157. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description............................. 85

Table 158. Register address map - embedded functions ................................................ 86

Table 159. PAGE_SEL register ................................................................. 88

Table 160. PAGE_SEL register description ......................................................... 88

LSM6DSO32X

List of tables

DS13607 - Rev 1

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LSM6DSO32X Datasheet(PDF) 155 Page - STMicroelectronics

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