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MCP39F511N Datasheet(PDF) 37 Page - Microchip Technology

Part # MCP39F511N
Description  Dual-Channel, Single-Phase Power-Monitoring IC with Calculation
PDF  61 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP39F511N Datasheet(HTML) 37 Page - Microchip Technology

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 2015-2018 Microchip Technology Inc.
DS20005473B-page 37
MCP39F511N
7.0
EVENT OUTPUT PINS/EVENT
CONFIGURATION REGISTER
7.1
Event Pins
The MCP39F511N device has two event pins that can
be configured in three possible configurations. These
configurations are:
1.
No event is mapped to the pin
2.
Voltage Surge, Voltage Sag, Over Current or
Over Power event is mapped to the pin. More
than one event can be mapped to the same pin.
3.
Manual control of two pins, independently. Pos-
sible only when no event is mapped to the pin.
These three configurations allow for the control of
external interrupts or hardware that is dependent on
the measured power, current or voltage. The Event
Configuration Register below describes how these
events and pins can be configured.
7.2
Limits
There are 6 limit registers associated with these
events:
• Voltage Sag Limit
• Voltage Surge Limit
• Over Current Limit, channel 1
• Over Power Limit, channel 1
• Over Current Limit, channel 2
• Over Power Limit, channel 2
Each of these limits are compared to the respective
output registers of voltage, current and power, and
should have the same unit, e.g. 0.1V, 0.01W, etc.
7.3
Voltage Sag and Voltage Surge
Detection
The event alarms for Voltage Sag and Voltage Surge
work differently compared to the Over Current and
Over Power events, which are tested against every
computation cycle. These two event alarms are
designed to provide a much faster interrupt if the con-
dition occurs. Note that neither of these two events
have a respective Hold register associated with them,
since the detection time is less than one line cycle.
The calculation engine keeps track of a trailing mean
square of the input voltage, as defined by Equation 7-1:
EQUATION 7-1:
Therefore, at each data-ready occurrence, the value of
VSA is compared to the programmable threshold set in
the Voltage Sag Limit register and Voltage Surge Limit
register to determine if a flag should be set. If either of
these events are masked to either the Event1 or
Event2 pin, a logic-high interrupt will be given on these
pins.
The Sag or Surge events can be used to quickly
determine if a power failure has occurred in the system.
7.4
Calibration Status Events
The Event register contains eight bits that correspond
to the pass/fail of a calibration attempt issued through
the Auto-Calibrate Gain commands.
These commands can be used to calibrate all
single-point calibration outputs for both channels:
• Line Frequency
•Voltage
• Channel 1 Current
• Channel 1 Active Power
• Channel 1 Reactive Power
• Channel 2 Current
• Channel 2 Active Power
• Channel 2 Reactive Power
Bits 31-24 are status bits with a 1 representing a
calibration fail. These bits are reset to 0 when a
calibration command is successful for whichever
channel (or both) is being calibrated. For more
information
on
calibration,
see
Section 9.3
“Single-Point Gain Calibrations at Unity Power
Factor”.
V
SA
2f
LINE
f
SAMPLE
--------------------------V
n
n
f
SAMPLE
2f
LINE
--------------------------
–
1
–
=
0
2
=



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