HMC524ALC3BTR-R5 datasheet(22/24 Pages) AD

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HMC524ALC3B

Data Sheet

Rev. A | Page 22 of 24

APPLICATIONS INFORMATION

Figure 80 shows the typical application circuit for the

HMC524ALC3B. To select the appropriate sideband, an external

90° hybrid coupler is needed. For applications not requiring

operation to dc, use an off chip dc blocking capacitor. For

applications that require the LO signal at the output to be

suppressed, use a bias tee or RF feed as shown in Figure 80.

Ensure that the source or sink current used for LO suppression

is <2 mA for each IF port to prevent damage to the device. The

common-mode voltage for each IF port is 0 V.

To select the upper sideband when using as an upconverter,

connect the IF1 pin to the 90° port of the hybrid and connect

the IF2 pin to the 0° port of the hybrid. To select the lower

sideband, connect the IF1 pin to the 0° port of the hybrid and

connect the IF2 pin to the 90° port of the hybrid. The input is

from the sum port of the hybrid, and the difference port is 50 Ω

terminated.

To select the upper sideband (low-side LO) when using as a

downconverter, connect the IF1 pin to the 0° port of the hybrid

and connect the IF2 pin to the 90° port of the hybrid. To select

the lower sideband (high-side LO), connect the IF1 pin to the

90° port of the hybrid and connect the IF2 pin to the 0° port of

the hybrid. The output is from the sum port of the hybrid, and

the difference port is 50 Ω terminated.

90°HYBRID

IF1

IF2

HMC524ALC3B EVALUATION BOARD

50Ω

SUPPLY

FOR IF1

SUPPLY

FOR IF2

BIAS TEE/

DC FEED FOR IF2

BIAS TEE/

DC FEED FOR IF1

DC BLOCKING

CAPACITORS

EXTERNAL

90° HYBRID

NOTES

1. DASHED SECTIONS ARE OPTIONAL AND MEANT FOR LO NULLING.

Figure 80. Typical Application Circuit Evaluation Board Information

The EV1HMC524ALC3B evaluation PCB used in the application

must use RF circuit design techniques. Signal lines must have 50 Ω

impedance, and connect the package ground leads and exposed

pad directly to the ground plane similarly to Figure 82. Use a

sufficient number of via holes to connect the top and bottom

ground planes. The evaluation circuit board shown in Figure 82 is

available from Analog Devices, Inc., upon request.

LAYOUT

Solder the exposed pad on the underside of the HMC524ALC3B

to a low thermal and electrical impedance ground plane. This

pad is typically soldered to an exposed opening in the solder mask

on the evaluation board. Connect these ground vias to all other

ground layers on the evaluation board to maximize heat dissipation

from the device package. Figure 81 shows the PCB land pattern

footprint for the EV1HMC524ALC3B evaluation board.

Figure 81. PCB Land Pattern Footprint of the EV1HMC524ALC3B

HMC524ALC3BTR-R5 Datasheet(PDF) 22 Page - Analog Devices

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