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MCP3461RT-E/ST Datasheet(PDF) 18 Page - Microchip Technology |
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MCP3461RT-E/ST Datasheet(HTML) 18 Page - Microchip Technology |
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18 / 118 page ![]() MCP3461/2/4R DS20006404C-page 18 2020-2021 Microchip Technology Inc. Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, MCLK = 4.9152 MHz, VIN = -0.5 dBFS at 50 Hz, VREF = AVDD, ADC_MODE[1:0] = 11. All other registers are set to default value. Histogram ticks are centered at their bin center. FIGURE 2-19: SINAD Distribution Histogram. FIGURE 2-20: THD Distribution Histogram. FIGURE 2-21: SFDR Distribution Histogram. FIGURE 2-22: SNR Distribution Histogram, Internal VREF. FIGURE 2-23: SINAD Distribution Histogram, Internal VREF. FIGURE 2-24: THD Distribution Histogram, Internal VREF. 0 5 10 15 20 25 30 35 40 45 Signal-to-Noise-and-Distortion Ratio (dB) 33 devices x 3 lots Bin Size: 0.05 dB 0 2 4 6 8 10 12 14 16 18 20 Total Harmonic Distortion (dBc) 33 devices x 3 lots Bin Size: 0.5 dB 0 5 10 15 20 25 Spurious-Free Dynamic Range (dBc) 33 devices x 3 lots Bin Size: 1.0 dB 0 5 10 15 20 25 30 35 40 Signal-to-Noise Ratio (dB) 33 devices x 3 lots Bin Size: 0.05 dB 0 5 10 15 20 25 30 35 40 Signal-to-Noise-and-Distortion Ratio (dB) 33 devices x 3 lots Bin Size: 0.05 dB 0 5 10 15 20 25 30 35 Total Harmonic Distortion (dBc) 33 devices x 3 lots Bin Size: 0.5 dB |
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