MCP3462T-ESLASHST datasheet(24/108 Pages) MICROCHIP

24 / 108 page

MCP3461/2/4

DS20006180D-page 24

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3.1

Differential Reference Voltage

Inputs: REFIN+, REFIN-

REFIN+ pin is the noninverting differential reference

input (VREF+).

REFIN- pin is the inverting differential reference input

(VREF-).

For single-ended reference applications, the REFIN-

pin should be directly connected to AGND.

The differential reference voltage pins must respect

this condition at all times: 0.6V ≤ VREF ≤ AVDD. The

differential reference voltage input is given by

Equation 3-1:

EQUATION 3-1:

For optimal ADC accuracy, appropriate bypass

capacitors should always be placed between REFIN+

and AGND. Using 0.1 µF and 10 µF ceramic capacitors

helps with decoupling the reference voltage around the

sampling frequency (which would lead to aliasing noise

in the base band). These bypass capacitors are not

mandatory for correct ADC operation, but removing

these capacitors may degrade accuracy of the ADC.

3.2

Analog Inputs (CHn): Differential

or Single-Ended

The CHn pins are the analog input signal pins for the

ADC. Two analog multiplexers are used to connect the

CHn pins to the VIN+/VIN- analog inputs of the ADC.

Each multiplexer independently selects one input to be

connected to an ADC input (VIN+ or VIN-). Each CHn

pin can either be connected to the VIN+ or VIN- inputs

of the ADC. This multiplexer selection is controlled by

either the MUX register in MUX mode or the SCAN

on the multiplexer structure.

When the input is selected by the multiplexer, the

differential (VIN) and Common-Mode Voltage (VINCOM)

at the ADC inputs are defined by Equation 3-2.

EQUATION 3-2:

The input signal level is multiplied by the internal

programmable analog gain at the front end of the



modulator. For single-ended input measurements, the

user can select VIN- to be internally connected to AGND.

The differential input voltage should not exceed an

absolute of ±VREF/GAIN for accurate measurement. If

the input is out of range, the converter output code will

be saturated or overloaded depending on how the

output data format (DATA_FORMAT[1:0]) is selected.

See Section 5.6 “ADC Output Data Format” for

further information on the ADC output coding.

The absolute voltage range on each of the analog

signal input pins is from AGND – 0.1V to VDD + 0.1V.

Any voltage above or below this range will cause leak-

age currents through the Electrostatic Discharge (ESD)

diodes at the input pins. This ESD current can cause

unexpected

performance

the

device.

The

Common-mode of the analog inputs should be chosen

such that both the differential analog input range and

the absolute voltage range on each pin are within the

specified operating range defined in the Electrical

Characteristics table.

3.3

SPI Serial Interface

Communication pins

The SPI interface is compatible with both SPI Mode 0,0

and 1,1.

3.3.1

CHIP SELECT (CS)

This is the SPI chip select pin that enables/disables the

SPI serial communication. The CS falling edge initiates

the serial communication and the rising edge

terminates the communication. No communication can

take place when this pin is in Logic High state. This

input is Schmitt Triggered.

3.3.2

SERIAL DATA CLOCK (SCK)

This is the serial clock input pin for SPI communication.

This input has Schmitt Trigger structure. The maximum

SPI clock speed is 20 MHz. Data are clocked into the

device on the rising edge of SCK. Data are clocked out

of the device on the falling edge of SCK. The device

interface is compatible with both SPI Mode 0,0 and 1,1.

SPI modes can be changed when CS is in Logic High

state.

SCK and MCLK are two different and asynchronous

clocks; SCK is only required when a communication

happens, while MCLK is continuously required when

the part is converting analog inputs.

3.3.3

SERIAL DATA OUTPUT PIN (SDO)

This pin is used for the SPI Data Output (SDO). The

SDO data are clocked out on the falling edge of SCK.

This pin stays high-impedance under the following

conditions:

• When CS pin is logic high.

• During the whole SPI write or Fast command

communication period, after the SPI COMMAND

byte has been transmitted.

• After the two device address bits in the command

have been transmitted if the device address in the

command is not matching an internal chip device

address.

VREF

VREF+ VREF-

–

VIN

VIN+ VIN-

–

VINCOM

VIN+ VIN-

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