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MCP3462T-E/ST Datasheet(PDF) 68 Page - Microchip Technology |
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MCP3462T-E/ST Datasheet(HTML) 68 Page - Microchip Technology |
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68 / 108 page  MCP3461/2/4 DS20006180D-page 68 2019-2021 Microchip Technology Inc. If the COMMAND byte defines a static read of the ADCDATA register (address: 0x0), the ADC data will be present on SDO and will be updated continuously at each read. In this case, when a data ready interrupt happens within a read, the data are not corrupted and will be updated to a new value after the old value has been completely read. The ADC register contains a double buffer that prevents data from being corrupted while reading them. The part will be able to stream out- put data continuously, with no additional command, if the communication is not stopped with a CS rising edge. Figure 6-10 represents the continuous streaming of incoming ADCDATA, through the SPI port, with both SPI Modes 0,0 and 1,1. FIGURE 6-10: Continuous ADC Read (Data Streaming) with SPI Mode 0,0 and 1,1. Don’t Care Don’t Care SPI Mode 0,0; ADC Data Format: 32-Bit Don’t care SCK SDI SDO CS DATA0[31] Hi-Z Device Latches SDI on Rising Edge Device Latches SDO on Falling Fdge Don’t Care Hi-Z Device Latches SDI on Rising Edge Device Latches SDO on Falling Edge R/W Don’t care SCK SDI SDO CS Don’t Care SCK SDI SDO CS IRQ DATA1[31] DATA0[31] The Falling Edge After Read Start Clears the DR Interrupt on IRQ Pin SD OChanges Synchronously with the IRQ Falling Edge (DR interrupt flag) only when MS b is Present on SDO DR Interrupt (DATA1 is ready) The Falling Edge After Read Start Clears the DR Interrupt on IRQ Pin DATA0[0] SPI Mode 1,1; ADC Data Format: 32-Bit IRQ Read Start Read Start Read Start Read Start DR Interrupt (DATA1 is ready) The Falling Edge After Read Start Clears the DR Interrupt on IRQ Pin The Falling Edge After Read Start Clears the DR Interrupt on IRQ Pin timing> tDOD R timing> tDOD R |
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