ACE24AC08C datasheet(7/20 Pages) ACE

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ACE24AC08C

Two-wire Serial EEPROM

VER 1.1

Read Operations

The read command is similar to the write command except the 8th read/write bit in address word is set to

“1”. The three read operation modes are described as follows:

CURRENT ADDRESS READ

The EEPROM internal address word counter maintains the last read or write address plus one if the

power supply to the device has not been cut off. To initiate a current address read operation, the

microcontroller issues a START bit and a valid device address word with the read/write bit (8th) set to

“1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An

8-bit data word will then be serially clocked out. The internal address word counter will then

automatically increase by one. For current address read the micro-controller will not issue an

ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after

the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode.

SEQUENTIAL READ

The sequential read is very similar to current address read. The micro-controller issues a START bit

and a valid device address word with read/write bit (8th

) set to “1”. The EEPROM will response with

an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially

clocked out. Meanwhile the internally address word counter will then automatically increase by one.

Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock

cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the

ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the

incremented internal address counter. If the micro-controller needs another data, it sends out an

ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked

out.

This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE

signal after receiving a new data word. When the internal address counter reaches its maximum

valid address, it rolls over to the beginning of the memory array address. Similar to current address

read, the micro-controller can terminate the sequential read by not acknowledging the last data word

received, but sending a STOP bit afterwards instead.

RANDOM READ

Random read is a two-steps process. The first step is to initialize the internal address counter with a

target read

address using a “dummy write” instruction. The second step is a current address read.

To initialize the internal address counter with a target read address, the micro-controller issues a

START bit first, follows by a valid device address with the read/write bit (8th

) set to “0”. The EEPROM

will then acknowledge. The micro-controller will then send the address word. Again the EEPROM will

acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs

a current address read instruction to read the data. Note that once a START bit is issued, the

EEPROM will reset the internal programming process and continue to execute the new instruction -

which is to read the current address.

ACE24AC08C Datasheet(PDF) 7 Page - ACE Technology Co., LTD.

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