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M030GD2AE Datasheet(PDF) 49 Page - Nuvoton Technology Corporation |
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M030GD2AE Datasheet(HTML) 49 Page - Nuvoton Technology Corporation |
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49 / 118 page  M030G/M031G Series May 31, 2021 Page 49 of 118 Rev 1.00 6.2.6 SRAM Memory Organization This chip supports embedded 4/8 Kbytes size SRAM: Supports 4/8 Kbytes SRAM Supports byte / half word / word write Supports oversize response error Figure 6.2-8 shows the M030G/M031G series SRAM organization. The address between 0x2000_2000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal memory addresses. 0x2000_0000 0x3FFF_FFFF 8K byte SRAM bank0 Reserved 8K byte device 4K byte SRAM bank0 Reserved 4K byte device 0x2000_1000 0x2000_2000 Figure 6.2-8 SRAM Memory Organization 6.2.7 Chip Bus Matrix This chip supports Bus Matrix to manage the access arbitration between masters. The access arbitration uses round-robin algorithm as the bus priority. Cortex ® -M0 PDMA FLASH SRAM APB0 APB1 AHB (ctrl) M0 M1 S0 S1 S2 S3 S4 Figure 6.2-9 NuMicro® M030G/M031G Bus Matrix Diagram |
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