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R7G4HML3-6-STYVS1-R Datasheet(PDF) 6 Page - M-System Co.,Ltd. |
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R7G4HML3-6-STYVS1-R Datasheet(HTML) 6 Page - M-System Co.,Ltd. |
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6 / 9 page ![]() MODEL: R7G4HML3-6-STYVS1 R7G4HML3-6-STYVS1 SPECIFICATIONS ES-7772-I Rev.1 Page 6/9 https://www.m-system.co.jp/ RESPONSE TIME Response time of analog input module is time from when 0 to 100% stepwise signal change is applied to the analog module till when the communication ASIC of the module (slave) transmits 90% of input signal. Response time of analog output module is time form when 0 to 100% stepwise signal change is received by the communication ASIC of the module (slave) till when the analog output signal reaches 90%. TCOM: MECHATROLINK-III transmission cycle configured by a host device. MECHATROLINK-III transmission cycle vavies depends on system and configuration. TINP: Input module response time ≤ Input Delay time (Ta) + Conversion rate*1 (Tb) + input internal processing delay time (Tc) (two transmission cycle) T0UT: Output module response time ≤ Output internal processing delay time (Td) (one minimum transmission cycle the unit can handle) + Conversion rate (Te) + Output Delay time (Tf) *1. Conversion rate x Averaging E.g. 1. Averaging (1), sync signal input frequency of 50 Hz, transmission cycle of 1 msec. Input module response time (TINP): Input Delay time (100 msec.) + Conversion rate (20 msec.) × Averaging (1) + internal processing delay time (1 msec. x 2) = 122 [msec.] Output module response time (T0UT): Output internal processing delay time (0.125 msec.) + Conversion rate (0.20 msec.) + Output Delay time (0.25 msec.) = 0.575 [msec.] INPUT MODULE OUTPUT MODULE MECHATROLINK-III TRANSMISSION CYCLE TRANSMISSION FROM SLAVE COMMUNICATION ASIC RECEIVED BY SLAVE COMMUNICATION ASIC TINP TRANSMISSION TO A HOST (MASTER) Tb Tc Ta TOUT Te Tf Td TCOM TRANSMISSION FROM A HOST (MASTER) |
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