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MPC5602PEF0MLL4R Datasheet(PDF) 55 Page - NXP Semiconductors |
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MPC5602PEF0MLL4R Datasheet(HTML) 55 Page - NXP Semiconductors |
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55 / 95 page  MPC5602P Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 55 3.12 FMPLL electrical characteristics Table 25. Input clock characteristics Symbol Parameter Value Unit Min Typ Max fOSC SR Oscillator frequency 4 — 40 MHz fCLK SR Frequency in bypass — — 64 MHz trCLK SR Rise/fall time in bypass — — 1 ns tDC SR Duty cycle 47.5 50 52.5 % Table 26. FMPLL electrical characteristics Symbol C Parameter Conditions1 1 VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified Value Unit Min Max fref_crystal fref_ext D PLL reference frequency range2 2 Considering operation with PLL not bypassed. Crystal reference 4 40 MHz fPLLIN D Phase detector input frequency range (after pre-divider) —4 16 MHz fFMPLLOUT D Clock frequency range in normal mode — 16 64 MHz fFREE P Free-running frequency Measured using clock division—typically /16 20 150 MHz tCYC D System clock period — — 1 / fSYS ns fLORL D Loss of reference frequency window3 3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode. Lower limit 1.6 3.7 MHz fLORH D Upper limit 24 56 fSCM D Self-clocked mode frequency4,5 — 20 150 MHz CJITTER T CLKOUT period jitter6,7,8,9 Short-term jitter10 fSYS maximum 44 % fCLKOUT Long-term jitter (average over 2 ms interval) fPLLIN =16MHz (resonator), fPLLCLK at 64 MHz, 4000 cycles —10 ns tlpll D PLL lock time11, 12 — — 200 µs tdc D Duty cycle of reference — 40 60 % fLCK D Frequency LOCK range — 66 % fSYS fUL D Frequency un-LOCK range — 18 18 % fSYS fCS D Modulation depth Center spread ±0.25 ±4.013 %fSYS fDS D Down spread 0.5 8.0 fMOD D Modulation frequency14 — — 70 kHz |
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