Figure 4-4. Bottom Layer Copper and Vias for Thermal Pad Array (mm)

Note:  The contract manufacturer has latitude to modify the solder paste stencil for manufacturability reasons. The

solder paste stencil covers 65% to 80% of the thermal pad and should not allow solder to be applied to the thermal

vias under the QFN package using any method they deem appropriate. At the pin, the dimension of the paste mask

should be 5-10% smaller than the PCB copper feature. Minimize the extension of the solder mask outside the edge of

the package. Any design should be subject to system validation and qualification prior to commitment to mass

production of field deployment. Use a 5 mil stencil.

PD70224

Package Information

Datasheet

DS00003575C-page 15