LPC47N237-MD datasheet(39/138 Pages) SMSC

39 / 138 page

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC DS – LPC47N237

Page 39

Revision 0.3 (10-26-04)

DATASHEET

This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with

a 12 bit character.

Character times are calculated by using the RCLK input for a clock signal (this makes the delay

proportional to the baudrate).

When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one

character from the RCVR FIFO.

When a timeout interrupt has not occurred the timeout timer is reset after a new character is received

or after the CPU reads the RCVR FIFO.

When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT

interrupts occur as follows:

The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as

soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT

FIFO while servicing this interrupt) or the IIR is read.

The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time

whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time

in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be

immediate, if it is enabled.

Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received

data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register

empty interrupt.

8.5

FIFO Polled Mode Opertion

With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of

operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the

polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the

LSR. LSR definitions for the FIFO Polled Mode are as follows:

Bit 0=1 as long as there is one byte in the RCVR FIFO.

Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as

when in the interrupt mode, the IIR is not affected since EIR bit 2=0.

Bit 5 indicates when the XMIT FIFO is empty.

Bit 6 indicates that both the XMIT FIFO and shift register are empty.

Bit 7 indicates whether there are any errors in the RCVR FIFO.

There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the

RCVR and XMIT FIFOs are still fully capable of holding characters.

Table 8.3 – UART Baud Rates

DESIRED

BAUD RATE

DIVISOR USED TO

GENERATE 16X CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

(NOTE 8.2

)

HIGH

SPEED BIT

(NOTE 8.3

)

2304

0.001

1536

110

1047

134.5

857

0.004

150

768

300

384

600

192

LPC47N237-MD Datasheet(PDF) 39 Page - SMSC Corporation

LPC47N237-MD Datasheet(HTML) 39 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL