LPC47N237-MD datasheet(49/138 Pages) SMSC

49 / 138 page

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC DS – LPC47N237

Page 49

Revision 0.3 (10-26-04)

DATASHEET

If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then

the write can complete when nWAIT goes inactive high.

If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before

changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is

determined inactive.

Write Sequence of operation

The host initiates an I/O write cycle to the selected EPP register.

If WAIT is not asserted, the chip must wait until WAIT is asserted.

The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.

Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and

the WRITE signal is valid.

Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip

may begin the termination phase of the cycle.

a.) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination

phase. If it has not already done so, the peripheral should latch the information byte now.

b.) The chip latches the data from the internal data bus for the PData bus and drives the sync that

indicates that no more wait states are required followed by the TAR to complete the write cycle.

Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied

and acknowledging the termination of the cycle.

Chip may modify nWRITE and nPDATA in preparation for the next cycle.

9.2.3

EPP 1.9 Read

The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts

wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The

read cycle can complete under the following circumstances:

If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can

complete when nWAIT goes inactive high.

If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before

changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT

is determined inactive.

Read Sequence of Operation

The host initiates an I/O read cycle to the selected EPP register.

If WAIT is not asserted, the chip must wait until WAIT is asserted.

The chip tri-states the PData bus and deasserts nWRITE.

Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the

nWRITE signal is valid.

Peripheral drives PData bus valid.

Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination

phase of the cycle.

a.) The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB

or nADDRSTRB. This marks the beginning of the termination phase.

b.) The chip drives the sync that indicates that no more wait states are required and drives valid data

onto the LAD[3:0] signals, followed by the TAR to complete the read cycle.

Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-

stated.

Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.

LPC47N237-MD Datasheet(PDF) 49 Page - SMSC Corporation

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