A7101CLTK2SLASHT0BC2 datasheet(7/24 Pages) NXP

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Product short data sheet

COMPANY PUBLIC

Rev. 3.1 — 10 September 2020

512331

7 of 24

NXP Semiconductors

A71CL

Plug & Trust Secure Element

Functional description

6.1 I2C Interface

The A71CL uses I2C as communication interface as described in the following section.

The A71CL commands are wrapped using the Smartcard I2 protocol (SCI2C). The

detailed documentation for the A71CL commands in the APDU Specification and SCI2C

encapsulation (Ref. 3) is available in NXP DocStore.

The A71CL has an I2C interface in slave mode, supporting data rates up to 400 kbit/s

operating in Fast-Mode (FM). The I2C interface is using the Smartcard I2C protocol as

defined in Ref. 3 which is based on SMBus. Depending on the interface pins state at boot,

see Section 7 for more details. The default I2C address after power-on-reset depends on

the bootup condition as shown in Table 5.

6.2 Automatic Communication Mode detection at Power on

The IC configures its interface according to the pin state as shown in the table below. The

host system must keep the voltage levels stable at these pins for at least 500

µs after

power-on-reset.

6.3

Power-saving modes

The device provides two power-saving operation modes, the SLEEP mode and the DEEP

SLEEP mode. These modes are activated via pad RST_N (DEEP SLEEP mode) or by the

device.

6.3.1 SLEEP mode

The SLEEP mode has the following properties:

• all internal clocks are frozen,

• CPU enters power saving mode with program execution being stopped,

• CPU registers keep their contents,

• RAM keeps its contents,

The A71CL enters automatically into SLEEP mode and also wakes up automatically from

SLEEP mode. In SLEEP mode, all internal clocks are stopped. The IOs hold the logical

states they had at the time IDLE was activated. During SLEEP mode security sensors

HVS, LVS, LTS, HTS, Light Sensors, Glitch Sensors and Active Shielding are disabled.

There are two ways to exit from the SLEEP mode:

• A reset signal on RST_N

• An External Interrupt edge triggered by a falling edge on I2C_SDA

Table 5.

I2C address

Value at startup

I2C address

IF0

IF1

I2C_SCL

I2C_SDA

Write

Read

n.a.

0x90

0x91

0x92

0x93

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