A7101CLTK2SLASHT0BC2BY datasheet(17/24 Pages) NXP

17 / 24 page

512330

All information provided in this document is subject to legal disclaimers.

Product short data sheet

COMPANY PUBLIC

Rev. 3.1 — 10 September 2020

512331

17 of 24

NXP Semiconductors

A71CL

Plug & Trust Secure Element

[1]

All appropriately marked values are typical values and only referenced for information. They are subject to change without notice.

[2]

tr is defined as rise time between 20% and 80% of the signal amplitude.

tf is defined as fall time between 80% and 20% of the signal amplitude.

[3]

During AC testing the inputs RST_N, I2C_SDA, I2C_SCL are driven at 0 V to +0.3 V for a LOW input level and at VDD −0.3 V to VDD for

a HIGH input level. Clock period and signal pulse (duty cycle) timing is measured at 50% of VDD.

[4]

tr is defined as rise time between 30% and 70% of the signal amplitude.

tf is defined as fall time between 70% and 30% of the signal amplitude.

13.3 EMC/EMI

EMC and EMI resistance according to IEC 61967-4.

tWKPIO

Pad LOW time for wake-up

from SLEEP mode

level triggered ext.int.

µs

edge triggered ext.int.

µs

tWKPRST RST_N LOW time for wake-up

from SLEEP mode

µs

tWKWT

Time from SLEEP mode

wake/up event to I2C_SDA

valid

100

CPIN

Pin capacitances RST_N,

I2C_SDA, /I2C_SCL

Test frequency = 1 MHz;

Tamb = 25 °C

Table 14.

Electrical AC characteristics of I2C_SDA, I2C_SCL, and RST_N[1];

VDD = 1.8 V ± 10% or 3 V ± 10% V; VSS = 0 V; Tamb = -40 to 90 °C

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Fig 5.

External clock drive and AC test timing reference points of I2C_SDA, I2C_SCL, and RST_N (see Table

note [3] and Table note [4]) in open drain mode

A7101CLTK2/T0BC2BY Datasheet(PDF) 17 Page - NXP Semiconductors

A7101CLTK2/T0BC2BY Datasheet(HTML) 17 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL