PLL102-15

Low Skew Output Buffe r

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 05/06/03 Page 8

REVISION HISTORY

06/20/01

Created from preliminary PLL102-05 and PLL102-04 Document

10/23/01

Removed Power Down mode in absence of REF (not supported in final version).

11/07/01

Added VDD = 3.3V in Electrical Specs for clarity.

11/29/01

Added Remark on REF clock absence on page 1

10/08/02

Change pass through modulation rate from 100kHz to 33kHz.

01/13/03

Changed Frequency range from “25-75MHz” to “25-60MHz” on Features section on page 1

Changed Max. of Output Frequency from “75” to “60” on page 4

Deleted “Fout < 50.0MHz” for Duty Cycle (Dt2) and “Measured at 60MHz” for Cycle to Cycle Jitter

(Tcyc -cyc) of Switching Characteristics section on page 4

05/06/03

Bonding diagram modification to P102-15 (ICS553 compatible)