PLL102-15

Low Skew Output Buffe r

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 05/06/03 Page 1

FEATURES

• Frequency range 25 ~ 60MHz.

• Internal phase locked loop will allow spread spec-

trum modulation on reference clock to pass to the

outputs (up to 33kHz SST modulation).

• Zero input - output delay.

• Less than 700 ps device - device skew.

• Less than 250 ps skew between outputs.

• Less than 200 ps cycle - cycle jitter.

• Output Enable function tri-state outputs.

• 3.3V operation.

• Available in 8 -Pin 150mil SOIC.

DESCRIPTIONS

The PLL102-15 is a high performance, low skew, low

jitter zero delay buffer designed to distribute high

speed clocks and is available in 8 -pin SOIC or TSSOP

package. It has four outputs that are synchronized with

the input. The synchronization is established via

CLKOUT feedback to the input of the PLL. Since the

skew b etween the input and output is less than

±350

ps, the device acts as a zero delay buffer.

PIN CONFIGURATION

Remark

If REF_IN clock is stopped for more than 10us after it has already been

provided to the chip, and after power-up, the output clocks will

disappear. In that instance, a full power-up reset is required in order

to reactivate the output clocks.

BLOCK DIAGRAM

1

2

3

4

VDD

5

6

7

8

CLK1

CLKOUT

GND

N/C

CLK3

CLK2

REF_IN

PLL

REF_IN

CLKOUT

CLK1

CLK2

CLK3