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PLL650-04ACLR Datasheet(PDF) 2 Page - PhaseLink Corporation |
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PLL650-04ACLR Datasheet(HTML) 2 Page - PhaseLink Corporation |
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2 / 6 page ![]() Preliminary PLL650-04 Low EMI Clock for 10/100 PHY and Gigabit Ethernet 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 05/31/05 Page 2 PIN DESCRIPTIONS Name Number Type Description XIN 1 I Crystal input to be connected to a 25MHz fundamental parallel mode crystal (CL=20pF). XOUT/SSTE 2 B Crystal connector. At power-up, the SSTE value that enables/disables the spread spectrum function is latched in. 120k Ω internal pull up resistor. GND 3,11,15,17 P Ground. VDD 4,6,20 P 3.3V power supply. CLKOUT_EN 5 I CLKOUT enable pin. Disables CLKOUT to tri-state if ‘low’ (logical 0). Internal 60k Ω pull-up resistor defaults it to ‘high’ (logical 1). CLKOUT 7,8,10,12,14 O CLKOUT outputs with selectable frequency through FS(0:1). CLKOUT can be modulated using SST to reduce EMI through SSTE. CLKOUT can be disabled to tri-state with CLKOUT_EN. FS0 13 TL Tri-level frequency selector pin (See selection table on p.1). 0: connected to GND, 1: connected to VDD, M: not connected. FS1 9 I Frequency selector pin (standard bi-level ‘1’ or ‘0’). See table on p.1. Internal 60k Ω pull-up resistor defaults it to ‘high’ (logical 1). 50 MHz 16 O 50 MHz output. This output is not modulated with Spread Spectrum. This output can be disabled to tri-state with 50M_EN. 25 MHz/25M_EN 18 B 25 MHz output, not modulated with Spread Spectrum. Bi-directional pin: at power-up, the input value 25M_EN is latched-in. If 25M_EN (25MHz output enable) is low, the pin will be disabled to tri-state after power-up, if 25M_EN is high, the out pin will be enabled and provide a 25 MHz output signal after power-up. Internal 60k Ω pull-up resistor defaults it to ‘high’ (logical 1). 50M_EN 19 I 50 MHz output enable pin. Disables the 50MHz output to tri-state if ‘low’ (logical 0). Internal 60k Ω pull-up resistor defaults it to ‘high’ (logical 1). FUNCTIONAL DESCRIPTION Selectable spread spectrum and output frequencies The PLL650-04 provides selectable spread spectrum modulation and selectable output frequencies for the CLKOUT signal. Selection is made by connecting specific pins to a logical “zero” or “one”, according to the frequency and spread spectrum selection tables shown on page 1. In order to reduce the number of pins on the chip, the PLL650-04 uses bi-directional pins that serve as inputs upon power-up, and as outputs as soon as the inputs have been latched. Pins 2 (SSTE) is a bi-directional pin used as input to enable/disable the spread spectrum modulation upon power-up, and used as XOUT crystal connection after the SSTE input signal has been latched. Pin 18 (25M_EN) is a bi-directional pin used to enable/disable the 25MHz output upon power-up. After the input signal has been latched, pin 18 will serve as 25 MHz output or will be disabled, depending on the power-up value of 25M_EN. |
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