Preliminary

PLL650-04

Low EMI Clock for 10/100 PHY and Gigabit Ethernet

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 05/31/05 Page 3

Connecting a selection pin to a logical “one”

The output enable and spread spectrum selection pins have an internal pull-up resistor (60k

Ω for all selection pins except for

pin 2 (SSTE), which has a 120k

Ω internal pull-up). This internal pull-up resistor will pull the input value to a logical “one” (pull-

up) by default, i.e. when no resistive load is connected between the pin and GND. No external pull-up resistor is therefore

required for connecting a logical “one” upon power-up. Note: when the output load presents a low impedance in comparison to

the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up to a logical “one”, and an

external pull-up resistor may be required.

Connecting a selection pin to a logical “zero”

Connecting the bi-directional pin to a logical “zero” does require the use of an external loading resistor between the pin and

GND that has to be sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V

(logical “zero”). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor

should however be kept as large as possible. In general, it is recommended to use an external resistor of around one sixth to

one quarter of the internal pull-up resistor (see Application Diagram). Note: when the output is used to drive a load presenting

an small resistance between the output pin and VDD, this resistance is in essence connected in parallel to the internal pull-up

resistor. In such a case, the external pull-down resistor may have to be dimensioned smaller to guarantee that the pin voltage

will be low enough achieve the desired logical “zero”. This is particularly true when driving 74FXX TTL components.

Selecting the output frequency (CLKOUT) with the tri-level selection pin

The CLKOUT frequency is selected with the tri-level FS(0:1) input pins, as per the frequency selection table on page 1. Unlike

the other bi-level selection pins, the tri-level input pins are in the “M” (mid) state when not connected. In order to connect a tri-

level pin to a logical “zero”, the pin must be connected to GND. Similarly, in order to connect a tri-level pin to a logical “one”, the

pin must be connected to VDD. No external pull-up or pull-down resistor is required with the tri-level selector pins.

APPLICATION DIAGRAM

Latch

Power Up

Reset

Jumper options

R

Clock Load

Latched

Input

Output

EN

VDD

R

up

Bi-directional pin

R

RB

NOTE: Rup=120k

Ω for SSTE (Pin2); Rup=60k Ω for 25M_EN (Pin18). R starts from 1 to 0 while RB starts from 0 to 1.

Internal to chip

External Circuitry