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AT25SL641

DS-25SL641–113F–12/2018

and does not effect the current cycle. The Read Data instruction allows clock rates from D.C to a maximum of fR (see AC

Electrical Characteristics).

Figure 7-11. Read Data Instruction

7.10

Fast Read (0Bh)

The Fast Read instruction is a high speed reading mode that can operate at the highest possible frequency of FR. The address

is latched on the rising edge of the SCK. After the 24-bit address, eight dummy clocks are shifted in as shown in Figure 7-12.

The dummy clocks allow the internal circuits the time required to set up the initial address. During the dummy clocks, the data

value on the SO pin is a “don’t care”. Data of each bit shifts out on the falling edge of SCK.

Figure 7-12. Fast Read Instruction (SPI Mode)

Fast Read in QPI Mode

When QPI mode is enabled, the number of dummy clock is configured by the Set Read Parameters (C0h) instruction to

accommodate a wide range applications with different needs for either maximum Fast Read frequency or minimum data

access latency. The number of dummy clock cycles can be configured as either 4, 6 or 8 by setting bits P[5:4] in the 8-

bit parameter of the Set Read Parameters (C0h) command as shown in Table 7-6, Encoding of the P[5:4] Bits. The

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