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SLG46855-AP Datasheet(PDF) 21 Page - Dialog Semiconductor |
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SLG46855-AP Datasheet(HTML) 21 Page - Dialog Semiconductor |
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21 / 199 page  Datasheet 17-Jun-2021 CFR0011-120-00 Revision 3.0 21 of 199 © 2021 Dialog Semiconductor SLG46855-A Auto Grade GreenPAK Programmable Mixed-Signal Matrix tpd Delay LATCH3, LATCH12 Second nRESET Low Q -- 25 -- 18 -- 12 ns tpd Delay LATCH3, LATCH12 Second nRESET Low nQ 26 -- 18 -- 13 -- ns tpd Delay LATCH3, LATCH12 Second nSET High Q 20 -- 14 -- 10 -- ns tpd Delay LATCH3, LATCH12 Second nSET High nQ -- 20 -- 14 -- 10 ns tpd Delay LATCH3, LATCH12 Second nSET Low Q 23 -- 16 -- 11 -- ns tpd Delay LATCH3, LATCH12 Second nSET Low nQ -- 22 -- 16 -- 11 ns tpd Delay 2-bit LUT 15 16 11 11 7 8 ns tpd Delay 3-bit LUT 16 17 11 12 8 8 ns tpd Delay 4-bit LUT 19 17 13 12 9 9 ns tpd Delay Multi-Function 3-bit LUT 18 21 13 15 9 11 ns tpd Delay Multi-Function 3-bit LUT, CNT Delay 46 47 33 34 23 24 ns tpd Delay Multi-Function 4-bit LUT 21 23 15 17 10 12 ns tpd Delay Multi-Function 4-bit LUT, CNT Delay 48 46 34 34 23 24 ns tpd Delay Edge detect 19 20 13 14 9 9 ns tw Width Edge detect 211 212 156 157 115 115 ns tpd Delay Edge detect Delayed 231 235 170 173 124 126 ns tpd Delay Ripple CNT CLK DOWN Q0 18 16 13 11 9 8 ns tpd Delay Ripple CNT CLK DOWN Q1 29 22 20 16 14 11 ns tpd Delay Ripple CNT CLK DOWN Q2 27 29 20 21 14 14 ns tpd Delay Ripple CNT CLK UP Q0 18 16 13 11 9 8 ns tpd Delay Ripple CNT CLK UP Q1 24 24 17 17 12 12 ns tpd Delay Ripple CNT CLK UP Q2 29 23 21 17 15 12 ns tpd Delay Ripple CNT nSET DOWN Q0 26 33 19 23 14 16 ns tpd Delay Ripple CNT nSET DOWN Q1 26 41 19 29 13 21 ns tpd Delay Ripple CNT nSET DOWN Q2 25 41 18 29 13 20 ns tpd Delay Ripple CNT nSET UP Q0 26 33 19 23 14 16 ns tpd Delay Ripple CNT nSET UP Q1 26 38 19 27 13 19 ns tpd Delay Ripple CNT nSET UP Q2 25 44 18 32 13 22 ns tpd Delay DFF Q 17 17 12 12 8 8 ns tpd Delay DFF nQ 18 16 13 11 9 8 ns tpd Delay DFF nRESET High Q -- 20 -- 14 -- 10 ns tpd Delay DFF nRESET High nQ 21 -- 15 -- 10 -- ns tpd Delay DFF nRESET Low Q -- 22 -- 16 -- 11 ns tpd Delay DFF nRESET Low nQ 23 -- 17 -- 12 -- ns tpd Delay DFF nSET High Q 21 -- 15 -- 10 -- ns tpd Delay DFF nSET High nQ -- 20 -- 14 -- 10 ns tpd Delay DFF nSET Low Q 23 -- 16 -- 12 -- ns Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued) Parameter Description Note VDD = 2.5 V VDD = 3.3 V VDD = 5 V Unit Rising Falling Rising Falling Rising Falling |
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