SLDN-40E1A

21

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BCD.20114_AF

The SLDN-40E1Ax modules have a power management bus interface that supports both communication and control. The power

management bus Power Management Protocol Specification can be obtained from www.power management bus.org. The modules

support a subset of version 1.1 of the specification (see Table 6 for a list of the specific commands supported). Most module

parameters can be programmed using Power management bus and stored as defaults for later use.

All communication over the module power management bus interface must support the Packet Error Checking (PEC) scheme. The

Power management bus master must generate the correct PEC byte for all transactions and check the PEC byte returned by the

module.

The module also supports the SMBALERT# response protocol whereby the module can alert the bus master if it wants to talk. For

more information on the SMBus alert response protocol, see the System Management Bus (SMBus) specification.

The module has non-volatile memory that is used to store configuration settings. Not all settings programmed into the device are

automatically saved into this non-volatile memory, only those specifically identified as capable of being stored can be saved (see

Table 6 for which command parameters can be saved to non-volatile storage).

For commands that set thresholds, voltages or report such quantities, the module supports the “Linear” data format among the

three data formats supported by Power management bus. The Linear Data Format is a two byte value with an 11-bit, two’s

complement mantissa and a 5-bit, two’s complement exponent. The format of the two data bytes is shown below:

The value is of the number is then given by

The SLDN-40E1Ax module can be addressed through the Power management bus using a device address. The module has 64

possible addresses (0 to 63 in decimal) which can be set using resistors connected from the ADDR0 and ADDR1 pins to SIG_GND.

Note that some of these addresses (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 12, 40, 44, 45, 55 in decimal) are reserved according to the

SMBus specifications and may not be useable. The address is set in the form of two octal (0 to 7) digits, with each pin setting one

digit. The ADDR1 pin sets the high order digit and ADDR0 sets the low order digit. The resistor values suggested for each digit are

shown in Table 4 (1% tolerance resistors are recommended). Note that if either address resistor value is outside the range specified

in Table 4, the module will respond to address 127.

Data Byte High

7 6 5 4 3

2 1 0 7 6 5 4 3 2 1 0

Data Byte Low

Exponent

MSB

Mantissa

MSB