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ZL30264 Datasheet(PDF) 39 Page - Microchip Technology |
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ZL30264 Datasheet(HTML) 39 Page - Microchip Technology |
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39 / 93 page ![]() ZL30264-ZL30267 Data Sheet 39 © 2021 Microchip Technology Inc. DS20006555A Register Name: OCEN1 Register Description: Output Clock Enable Register 1 Register Address: 05h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name OC8EN OC7EN OC6EN OC5EN OC4EN OC3EN OC2EN OC1EN Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Output Clock x Enable (OCxEN). Each of these bits enables and disables the corresponding output dividers, phase adjustment/alignment circuitry and start/stop circuitry. See section 5.6.1. 0 = Disabled 1 = Enabled Note: On Rev A devices at least one OCxEN bit must be set for each of the six output banks for proper operation. These bits should be set at or near the beginning of the configuration sequence. Register Name: OCEN2 Register Description: Output Clock Enable Register 2 Register Address: 06h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name — — — — — — OC10EN OC9EN Default 0 0 0 0 0 0 0 0 See the OCEN1 register description above. Register Name: OCMUX1 Register Description: Output Clock Mux Register 1 Register Address: 07h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name - - OCMUXC OCMUXB OCMUXA Default 0 0 0 0 0 0 0 0 Bits 5 to 4: Output Clock Mux C (OCMUXC[1:0]). Controls the high speed output mux for output group C (OC4 and OC5). 00 = APLL1 Integer divider 01 = APLL1 Fractional divider or bypass path (specified by ACR1.BYPASS) 10 = APLL2 Integer divider 11 = APLL2 Fractional divider or bypass path (specified by A2CR1.BYPASS) Bits 3 to 2: Output Clock Mux B (OCMUXB[1:0]). Controls the high speed output mux for output group B (OC3). 00 = APLL1 Integer divider 01 = APLL1 Fractional divider or bypass path (specified by ACR1.BYPASS) 10 = APLL2 Integer divider 11 = APLL2 Fractional divider or bypass path (specified by A2CR1.BYPASS) Bits 1 to 0: Output Clock Mux A (OCMUXA[1:0]). Controls the high speed output mux for output group A (OC1 and OC2). 00 = APLL1 Integer divider 01 = APLL1 Fractional divider or bypass path (specified by ACR1.BYPASS) 10 = APLL2 Integer divider 11 = APLL2 Fractional divider or bypass path (specified by A2CR1.BYPASS) |
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