ADMV8818SCCZ-EP-R2 datasheet(16/36 Pages) AD

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ADMV8818-EP

Enhanced Product

Rev. A | Page 16 of 36

SCLK

PARAMETERS AND

LOOKUP TABLE

INTERNAL STATE

MACHINE

START LOCATION

...

STOP LOCATION

SDO

SDI

SFL

FILTERS

Figure 36. Simplified SPI Diagram

SPI WRITE MODE

SPI write mode has five write groupings, WR0 through WR4 in

thought of as a small lookup table for SPI write mode. Each

grouping consists of the following:

•

RFIN switch position

•

RFIN switch set

•

RFOUT switch position

•

RFOUT switch set

•

HPF state

•

LPF state

See the Register Details section for an example of the write

grouping of WR0 (Register 0x020 and Register 0x021).

SWITCH POSITIONS

The RFIN switch position dictates where the HPF state bits are

assigned, and the RFOUT switch position dictates where the

LPF state bits are assigned. For example, in the WR0_SW write

group (Register 0x020), when SW_IN_WR0 is set for Band 1 and

SW_OUT_WR0 is set for Band 2, HPF_WR0 and LPF_WR0

(Register 0x021) are applied to HPF 1 and LPF 2, respectively.

SWITCH SET

The RFIN switch set bit is used to determine if the RFIN switch

position is moved to that setting. Similarly, the RFOUT switch

set bit is used to determine if the RFOUT switch position is moved

to that setting. This functionality is useful for configuring a filter to

a known state and leaving the switch position unchanged (switch

set bits low). For most applications, the switch set bits are high.

FILTER SETTINGS

Each high-pass filter and low-pass filter contains 16 states (4 bits).

A value of zero corresponds to setting the f3dB of the filter to its

lowest possible frequency. Conversely, a value of 15 corresponds to

setting the f3dB of the filter to its highest possible frequency.

WRITE GROUP PRIORITY

In SPI write mode, because there are five write groupings, it is

possible that multiple RFIN switch set bits or RFOUT switch

set bits are high. The behavior of the switches depends on the

type of SPI transaction, either streaming or single instruction.

In general, there are two types of SPI streaming transactions,

Endian register ascending order and descending order. The

ADMV8818-EP supports the ascending order only. To enable

SPI streaming with Endian register ascending order, program

For SPI streaming transactions (recommended), the priority

order for the RFIN switch set bits and the RFOUT switch set

bits is WR0 to WR4.

The SPI streaming transaction for Register 0x020 to Register 0x029

then points to Address 0x020 and streams out 10 bytes of data.

The SPI streaming transaction is 96 bits in total (R/W bit +

15 address bits + 80 data bits).

An example of the priority order for an SPI streaming transaction

follows: if the switch set bits are high for both WR1 and WR2, the

resulting switch positions are the positions programmed in WR1.

For SPI single instruction transactions, the most recently

programmed RFIN switch set and RFOUT switch set takes

effect to move the switch positions. To use SPI single instruction

transactions, the switch register must be written first followed

by the filter setting register. For example, to use write grouping

WR0, Register 0x020 is written first using a 24-bit transaction

(R/W bit + 15 address bits + 8 data bits, followed by writing

FREQUENCY TERMINOLOGY

Because the ADMV8818-EP is designed to operate over a wide

frequency range, there is frequency dependent insertion loss

that results in a negative slope vs. frequency. Additionally,

depending upon the selected filter and the state, there may also

be ripple within the pass band. Given these characteristics, a proper

definition is necessary to establish a reference frequency (fREF)

from which the f3dB for each filter can be computed.

Analog Devices has found that a consistent methodology

for determining the fREF and f3dB is to rely on the group delay

performance of a filter. The following is the methodology used

for determining the ADMV8818-EP specifications:

1. Find the peak group delay (GDPEAK) and peak group delay

frequency (fPEAK) as the filter insertion loss (S21) begins to

roll off.

2. For a low-pass filter, divide fPEAK by 2 to find the average

frequency (fAVG). For a high-pass filter, multiply fPEAK by 2.

Once fAVG is calculated, determine the group delay at this

frequency. Generally, the group delay is flat and approximately

equal to the average at this particular frequency (fAVG).

3. Take the mathematical mean of the group delay from Step 1

and Step 2 to find the reference group delay (GDREF), and

then find the corresponding fREF and reference insertion

loss (ILREF) for this group delay.

4. Subtract 3 dB from the ILREF to find the 3 dB insertion loss

(IL3dB), and then find the corresponding f3dB.

SPI FAST LATCH MODE

The ADMV8818-EP has a 128 state lookup table and an

internal state machine that is useful for quickly changing filter

states in SPI fast latch mode. When the SFL pin is high, SPI fast

ADMV8818SCCZ-EP-R2 Datasheet(PDF) 16 Page - Analog Devices

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