ADV7322KSTZ1 datasheet(39/88 Pages) AD

39 / 88 page

Preliminary Technical Data

ADV7322

Rev. PrA | Page 39 of 88

INPUT CONFIGURATION

Note that the ADV7322 defaults to simultaneous standard

definition and progressive scan upon power-up (Address[0x01]:

Input Mode = 011).

STANDARD DEFINITION ONLY

Address[0x01]: Input Mode = 000

The 8-bit multiplexed input data is input on Pins S7 to S0 (or

Pins Y7 to Y0, depending on Register Address 0x01, Bit 7), with

S0 being the LSB in 8-bit input mode (see Table 21). Input

standards supported are ITU-R BT.601/656. In 16-bit input

mode, the Y pixel data is input on Pins S7 to S0 and CrCb data

is input on Pins Y7 to Y0 (see Table 21).

16-Bit Mode Operation

When Register 0x01 Bit 7 = 0, CrCb data is input on the Y bus

and Y data is input on the S bus. When Register 0x01 Bit 7 = 1,

CrCb data is input on the C bus and Y data is input on Y bus.

The 27 MHz clock input must be input on Pin CLKIN_A. Input

sync signals are input on the S_VSYNC, S_HSYNC, and

S_BLANK pins.

Table 21. SD 8-Bit and 16-Bit Configuration

Configuration

Parameter

8-Bit Mode

16-Bit Mode

Y Bus

CrCb

S Bus

656/601, YCrCb

C Bus

Y Bus

656/601, YCrCb

S Bus

C Bus

CrCb

MPEG2

DECODER

CLKIN_A

S[7:0] OR Y[7:0]*

27MHz

YCrCb

ADV7322

*SELECTED BY ADDRESS 0x01 BIT 7

S_VSYNC,

S_HSYNC,

S_BLANK

Figure 48. SD Only Input Mode

PROGRESSIVE SCAN ONLY OR HDTV ONLY

Address[0x01]: Input Mode = 001 or 010, Respectively

YCrCb progressive scan, HDTV, or any other HD YCrCb data

can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data is

input on Pins Y7 to Y0 and the CrCb data is input on Pins C7 to

C0. In 4:4:4 input mode, Y data is input on Pins Y7 to Y0,

Cb data is input on Pins C7 to C0, and Cr data is input on Pins

S7 to S0. If the YCrCb data does not conform to SMPTE 293M

(525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i], SMPTE

296M[720p], SMPTE 240M(1035i) or BTA-T1004/1362, the

async timing mode must be used. RGB data can only be input in

4:4:4 format in PS input mode or in HDTV input mode when

HD RGB input is enabled. G data is input on Pins Y7 to Y0, R

data is input on Pins S7 to S0, and B data is input on Pins C7 to

C0. The clock signal must be input on Pin CLKIN_A.

MPEG2

DECODER

CLKIN_A

C[7:0]

S[7:0]

Y[7:0]

INTERLACED TO

PROGRESSIVE

YCrCb

27MHz

ADV7322

P_VSYNC,

P_HSYNC,

P_BLANK

Figure 49. Progressive Scan Input Mode

SIMULTANEOUS STANDARD DEFINITION AND

PROGRESSIVE SCAN OR HDTV

Address[0x01]: Input Mode 011 (SD 8-Bit, PS 16-Bit) or 101

(SD and HD, SD Oversampled), 110 (SD and HD, HD

Oversampled), Respectively

YCrCb, PS, HDTV, or any other HD data must be input in 4:2:2

format. In 4:2:2 input mode, the HD Y data is input on Pins Y7

to Y0 and the HD CrCb data is input on Pins C7 to C0. If PS

4:2:2 data is interleaved onto a single 10-bit bus, Pins Y7 to Y0

are used for the input port. The input data is to be input at 27

MHz, with the data being clocked on the rising and falling edge

of the input clock. The input mode register at Address 0x01 is

set accordingly. If the YCrCb data does not conform to SMPTE

293M (525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i],

SMPTE 296M[720p], SMPTE 240M(1035i) or BTA-T1004, the

async timing mode must be used.

The 8- bit standard definition data must be compliant with

ITU-R BT.601/656 in 4:2:2 format. Standard definition data is

input on Pins S7 to S0, with S0 being the LSB. The clock input

for SD must be input on CLKIN_A and the clock input for

HD/PS must be input on CLKIN_B. Synchronization signals

are optional. SD syncs are input on Pins S_VSYNC, S_HSYNC,

and S_BLANK. HD syncs on Pins P_VSYNC, P_HSYNC, and

P_BLANK.

ADV7322KSTZ1 Datasheet(PDF) 39 Page - Analog Devices

ADV7322KSTZ1 Datasheet(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL